Lines Matching +full:mv88e6xxx +full:- +full:mdio +full:- +full:external
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/marvell,mv88e6xxx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell MV88E6xxx DSA switch family
10 - Andrew Lunn <andrew@lunn.ch>
13 The Marvell MV88E6xxx switch series has been produced and sold
22 - enum:
23 - marvell,mv88e6085
24 - marvell,mv88e6190
25 - marvell,mv88e6250
43 - items:
44 - const: marvell,turris-mox-mv88e6085
45 - const: marvell,mv88e6085
46 - items:
47 - const: marvell,turris-mox-mv88e6190
48 - const: marvell,mv88e6190
53 eeprom-length:
59 reset-gpios:
65 description: The switch provides an external interrupt line, but it is
69 interrupt-controller:
71 the different sub-blocks.
73 '#interrupt-cells':
79 mdio:
80 $ref: /schemas/net/mdio.yaml#
82 description: Marvell MV88E6xxx switches have an varying combination of
83 internal and external MDIO buses, in some cases a combined bus that
87 mdio-external:
88 $ref: /schemas/net/mdio.yaml#
90 description: Marvell MV88E6xxx switches that have a separate external
91 MDIO bus use this port to access external components on the MDIO bus.
95 const: marvell,mv88e6xxx-mdio-external
98 - compatible
101 - $ref: dsa.yaml#/$defs/ethernet-ports
104 - compatible
105 - reg
110 - |
111 #include <dt-bindings/gpio/gpio.h>
112 mdio {
113 #address-cells = <1>;
114 #size-cells = <0>;
116 ethernet-switch@0 {
119 reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
121 mdio {
122 #address-cells = <1>;
123 #size-cells = <0>;
125 sw_phy0: ethernet-phy@0 {
129 sw_phy1: ethernet-phy@1 {
133 sw_phy2: ethernet-phy@2 {
137 sw_phy3: ethernet-phy@3 {
142 ethernet-ports {
143 #address-cells = <1>;
144 #size-cells = <0>;
146 ethernet-port@0 {
149 phy-handle = <&sw_phy0>;
150 phy-mode = "internal";
153 ethernet-port@1 {
156 phy-handle = <&sw_phy1>;
157 phy-mode = "internal";
160 ethernet-port@2 {
163 phy-handle = <&sw_phy2>;
164 phy-mode = "internal";
167 ethernet-port@3 {
170 phy-handle = <&sw_phy3>;
171 phy-mode = "internal";
174 ethernet-port@5 {
177 phy-mode = "rgmii-id";
179 fixed-link {
181 full-duplex;
187 - |
188 #include <dt-bindings/interrupt-controller/irq.h>
189 mdio {
190 #address-cells = <1>;
191 #size-cells = <0>;
193 ethernet-switch@0 {
195 #interrupt-cells = <2>;
196 interrupt-controller;
197 interrupt-parent = <&gpio1>;
199 pinctrl-0 = <&switch_interrupt_pins>;
200 pinctrl-names = "default";
203 mdio {
204 #address-cells = <1>;
205 #size-cells = <0>;
207 switch0phy1: ethernet-phy@1 {
211 switch0phy2: ethernet-phy@2 {
215 switch0phy3: ethernet-phy@3 {
219 switch0phy4: ethernet-phy@4 {
223 switch0phy5: ethernet-phy@5 {
227 switch0phy6: ethernet-phy@6 {
231 switch0phy7: ethernet-phy@7 {
235 switch0phy8: ethernet-phy@8 {
240 mdio-external {
241 compatible = "marvell,mv88e6xxx-mdio-external";
242 #address-cells = <1>;
243 #size-cells = <0>;
245 phy1: ethernet-phy@b {
247 compatible = "ethernet-phy-ieee802.3-c45";
250 phy2: ethernet-phy@c {
252 compatible = "ethernet-phy-ieee802.3-c45";
256 ethernet-ports {
257 #address-cells = <1>;
258 #size-cells = <0>;
260 ethernet-port@0 {
262 phy-mode = "rgmii";
265 fixed-link {
266 full-duplex;
272 ethernet-port@1 {
274 phy-handle = <&switch0phy1>;
278 ethernet-port@2 {
280 phy-handle = <&switch0phy2>;
284 ethernet-port@3 {
286 phy-handle = <&switch0phy3>;
290 ethernet-port@4 {
292 phy-handle = <&switch0phy4>;
296 ethernet-port@5 {
298 phy-handle = <&switch0phy5>;
302 ethernet-port@6 {
304 phy-handle = <&switch0phy6>;
308 ethernet-port@7 {
310 phy-handle = <&switch0phy7>;
314 ethernet-port@8 {
316 phy-handle = <&switch0phy8>;
320 ethernet-port@9 {
321 /* 88X3310P external phy */
323 phy-handle = <&phy1>;
324 phy-mode = "xaui";
328 ethernet-port@a {
329 /* 88X3310P external phy */
331 phy-handle = <&phy2>;
332 phy-mode = "xaui";