Lines Matching +full:zynqmp +full:- +full:gem
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence MACB/GEM Ethernet controller
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
22 - enum:
23 - cdns,zynq-gem # Xilinx Zynq-7xxx SoC
24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
25 - const: cdns,gem # Generic
28 - items:
29 - enum:
30 - xlnx,versal-gem # Xilinx Versal
31 - xlnx,zynq-gem # Xilinx Zynq-7xxx SoC
32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
33 - const: cdns,gem # Generic
35 - items:
36 - enum:
37 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs
38 - cdns,sam9x60-macb # Microchip sam9x60 SoC
39 - microchip,mpfs-macb # Microchip PolarFire SoC
40 - const: cdns,macb # Generic
42 - items:
43 - enum:
44 - atmel,sama5d3-macb # 10/100Mbit IP on Atmel sama5d3 SoCs
45 - enum:
46 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs.
47 - const: cdns,macb # Generic
49 - enum:
50 - atmel,sama5d29-gem # GEM XL IP (10/100) on Atmel sama5d29 SoCs
51 - atmel,sama5d2-gem # GEM IP (10/100) on Atmel sama5d2 SoCs
52 - atmel,sama5d3-gem # Gigabit IP on Atmel sama5d3 SoCs
53 - atmel,sama5d4-gem # GEM IP (10/100) on Atmel sama5d4 SoCs
54 - cdns,np4-macb # NP4 SoC devices
55 - microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface
56 - microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface
57 - sifive,fu540-c000-gem # SiFive FU540-C000 SoC
58 - cdns,emac # Generic
59 - cdns,gem # Generic
60 - cdns,macb # Generic
62 - items:
63 - enum:
64 - microchip,sam9x7-gem # Microchip SAM9X7 gigabit ethernet interface
65 - microchip,sama7d65-gem # Microchip SAMA7D65 gigabit ethernet interface
66 - const: microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface
71 - description: Basic register set
72 - description: GEMGXL Management block registers on SiFive FU540-C000 SoC
83 clock-names:
86 - enum: [ ether_clk, hclk, pclk ]
87 - enum: [ hclk, pclk ]
88 - const: tx_clk
89 - enum: [ rx_clk, tsu_clk ]
90 - const: tsu_clk
92 local-mac-address: true
94 phy-mode: true
96 phy-handle: true
104 Recommended with ZynqMP, specify reset control for this
105 controller instance with zynqmp-reset driver.
107 reset-names:
110 fixed-link: true
115 power-domains:
118 cdns,refclk-ext:
125 cdns,rx-watermark:
131 rx-watermark corresponds to the number of SRAM buffer locations,
135 '#address-cells':
138 '#size-cells':
148 "^ethernet-phy@[0-9a-f]$":
150 $ref: ethernet-phy.yaml#
153 reset-gpios: true
155 magic-packet:
164 - compatible
165 - reg
166 - interrupts
167 - clocks
168 - clock-names
169 - phy-mode
172 - $ref: ethernet-controller.yaml#
174 - if:
179 const: sifive,fu540-c000-gem
188 - |
193 cdns,rx-watermark = <0x44>;
194 phy-mode = "rmii";
195 local-mac-address = [3a 0e 03 04 05 06];
196 clock-names = "pclk", "hclk", "tx_clk";
198 #address-cells = <1>;
199 #size-cells = <0>;
201 ethernet-phy@1 {
203 reset-gpios = <&pioE 6 1>;
207 - |
208 #include <dt-bindings/power/xlnx-zynqmp-power.h>
209 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
210 #include <dt-bindings/phy/phy.h>
213 #address-cells = <2>;
214 #size-cells = <2>;
216 compatible = "xlnx,zynqmp-gem", "cdns,gem";
217 interrupt-parent = <&gic>;
223 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
224 #address-cells = <1>;
225 #size-cells = <0>;
227 power-domains = <&zynqmp_firmware PD_ETH_1>;
229 reset-names = "gem1_rst";
230 phy-mode = "sgmii";
232 fixed-link {
234 full-duplex;