Lines Matching +full:tx +full:- +full:internal +full:- +full:delay +full:- +full:ps
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - const: allwinner,sun8i-a83t-emac
17 - const: allwinner,sun8i-h3-emac
18 - const: allwinner,sun8i-r40-gmac
19 - const: allwinner,sun8i-v3s-emac
20 - const: allwinner,sun50i-a64-emac
21 - items:
22 - enum:
23 - allwinner,sun20i-d1-emac
24 - allwinner,sun50i-a100-emac
25 - allwinner,sun50i-h6-emac
26 - allwinner,sun50i-h616-emac0
27 - allwinner,sun55i-a523-gmac0
28 - const: allwinner,sun50i-a64-emac
36 interrupt-names:
42 clock-names:
45 phy-supply:
55 - compatible
56 - reg
57 - interrupts
58 - interrupt-names
59 - clocks
60 - clock-names
61 - resets
62 - reset-names
63 - phy-handle
64 - phy-mode
65 - syscon
68 - $ref: snps,dwmac.yaml#
69 - if:
74 - allwinner,sun8i-a83t-emac
75 - allwinner,sun8i-h3-emac
76 - allwinner,sun8i-v3s-emac
77 - allwinner,sun50i-a64-emac
81 allwinner,tx-delay-ps:
87 External RGMII PHY TX clock delay chain value in ps.
89 allwinner,rx-delay-ps:
95 External RGMII PHY TX clock delay chain value in ps.
97 - if:
102 - allwinner,sun8i-r40-gmac
106 allwinner,rx-delay-ps:
112 External RGMII PHY TX clock delay chain value in ps.
114 - if:
119 - allwinner,sun8i-h3-emac
120 - allwinner,sun8i-v3s-emac
124 allwinner,leds-active-low:
129 mdio-mux:
135 const: allwinner,sun8i-h3-mdio-mux
137 mdio-parent-bus:
142 "#address-cells":
145 "#size-cells":
151 description: Internal MDIO Bus
155 const: allwinner,sun8i-h3-mdio-internal
161 "^ethernet-phy@[0-9a-f]$":
163 $ref: ethernet-phy.yaml#
176 - clocks
177 - resets
190 - compatible
191 - mdio-parent-bus
192 - mdio@1
197 - |
199 compatible = "allwinner,sun8i-h3-emac";
203 interrupt-names = "macirq";
205 reset-names = "stmmaceth";
207 clock-names = "stmmaceth";
209 phy-handle = <&int_mii_phy>;
210 phy-mode = "mii";
211 allwinner,leds-active-low;
214 #address-cells = <1>;
215 #size-cells = <0>;
216 compatible = "snps,dwmac-mdio";
219 mdio-mux {
220 compatible = "allwinner,sun8i-h3-mdio-mux";
221 #address-cells = <1>;
222 #size-cells = <0>;
224 mdio-parent-bus = <&mdio1>;
227 compatible = "allwinner,sun8i-h3-mdio-internal";
229 #address-cells = <1>;
230 #size-cells = <0>;
232 ethernet-phy@1 {
236 phy-is-integrated;
242 #address-cells = <1>;
243 #size-cells = <0>;
248 - |
250 compatible = "allwinner,sun8i-h3-emac";
254 interrupt-names = "macirq";
256 reset-names = "stmmaceth";
258 clock-names = "stmmaceth";
260 phy-handle = <&ext_rgmii_phy>;
261 phy-mode = "rgmii";
262 allwinner,leds-active-low;
265 #address-cells = <1>;
266 #size-cells = <0>;
267 compatible = "snps,dwmac-mdio";
270 mdio-mux {
271 compatible = "allwinner,sun8i-h3-mdio-mux";
272 #address-cells = <1>;
273 #size-cells = <0>;
274 mdio-parent-bus = <&mdio2>;
277 compatible = "allwinner,sun8i-h3-mdio-internal";
279 #address-cells = <1>;
280 #size-cells = <0>;
282 ethernet-phy@1 {
291 #address-cells = <1>;
292 #size-cells = <0>;
294 ext_rgmii_phy: ethernet-phy@1 {
301 - |
303 compatible = "allwinner,sun8i-a83t-emac";
307 interrupt-names = "macirq";
309 reset-names = "stmmaceth";
311 clock-names = "stmmaceth";
312 phy-handle = <&ext_rgmii_phy1>;
313 phy-mode = "rgmii";
316 compatible = "snps,dwmac-mdio";
317 #address-cells = <1>;
318 #size-cells = <0>;
320 ext_rgmii_phy1: ethernet-phy@1 {