Lines Matching +full:0 +full:x54

54             <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
55             <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
60         mux-controls = <&mux1 0>;
63         #size-cells = <0>;
65         mdio@0 {
66             reg = <0x0>;
68             #size-cells = <0>;
72             reg = <0x8>;
74             #size-cells = <0>;
83         #size-cells = <0>;
85         mdio@0 {
86             reg = <0x0>;
88             #size-cells = <0>;
92             reg = <0x1>;
94             #size-cells = <0>;
103         reg = <0x1000 0x100>;
110                 <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */
111                 <0x3 0x40>; /* 1: reg 0x3, bit 6 */
112             idle-states = <MUX_IDLE_AS_IS>, <0>;
118         mux-controls = <&mux2 0>;
120         #size-cells = <0>;
124             #size-cells = <0>;
126             /* inputs 0..3 */
127             port@0 {
128                 reg = <0>;