Lines Matching full:nand
1 Freescale's NAND flash controller (NFC)
3 This variant of the Freescale NAND flash controller (NFC) can be found on
10 - #address-cells: shall be set to 1. Encode the nand CS.
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
14 rate and should not exceed maximum timing for any NAND memory chip
15 in a board stuffing. Typical NAND memory timings derived from this
23 Children nodes represent the available nand chips. Currently the driver can
24 only handle one NAND chip.
28 - nand-bus-width: see nand-controller.yaml
29 - nand-ecc-mode: see nand-controller.yaml
32 - nand-ecc-strength: supported strengths are 24 and 32 bit (see nand-controller.yaml)
33 - nand-ecc-step-size: step size equals page size, currently only 2k pages are
35 - nand-on-flash-bbt: see nand-controller.yaml
39 nfc: nand@400e0000 {
50 nand@0 {
53 nand-bus-width = <8>;
54 nand-ecc-mode = "hw";
55 nand-ecc-strength = <32>;
56 nand-ecc-step-size = <2048>;
57 nand-on-flash-bbt;