Lines Matching +full:clock +full:- +full:skip

5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
6 - reg : Address range of the mtd chip
7 - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
10 - bank-width : Width (in bytes) of the device.  If not present, the width
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
15   byte 0 TCLR  : CLE to RE delay in number of AHB clock cycles, only 4 bits
16                  are valid. Zero means one clockcycle, 15 means 16 clock
19   byte 2 THIZ  : number of HCLK clock cycles during which the data bus is
20                  kept in Hi-Z (tristate) after the start of a write access.
23   byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
26   byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
29   byte 5 TSET  : number of HCLK clock cycles to assert the address before the
32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
33 - nand-ecc-mode      : see nand-controller.yaml
34 - nand-ecc-strength  : see nand-controller.yaml
35 - nand-ecc-step-size : see nand-controller.yaml
37 Can support 1-bit HW ECC (default) or if stronger correction is required,
38 software-based BCH.
43 		compatible = "st,spear600-fsmc-nand";
44 		#address-cells = <1>;
45 		#size-cells = <1>;
50 		reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
52 		bank-width = <1>;
53 		nand-skip-bbtscan;