Lines Matching full:nand

7 title: Broadcom STB NAND Controller
15   The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
27   -- Additional SoC-specific NAND controller properties --
29   The NAND controller is integrated differently on the variety of SoCs on which
31   bits with which to control the 8 exposed NAND interrupts, as well as hardware
35   interesting ways, sometimes with registers that lump multiple NAND-related
39   register resources within the NAND controller node above.
58       - description: BCMBCA SoC-specific NAND controller
60           - const: brcm,nand-bcm63138
65       - description: iProc SoC-specific NAND controller
67           - const: brcm,nand-iproc
70       - description: BCM63168 SoC-specific NAND controller
72           - const: brcm,nand-bcm63168
73           - const: brcm,nand-bcm6368
85       enum: [ nand, flash-dma, flash-edu, nand-cache, nand-int-base, iproc-idm, iproc-ext ]
90       - description: NAND CTLRDY interrupt
103     description: reference to the clock for the NAND controller
106     const: nand
108   brcm,nand-has-wp:
118       Use this property when WP pin is not physically wired to the NAND chip.
124   "^nand@[a-f0-9]$":
126     $ref: raw-nand-chip.yaml
131       nand-ecc-step-size:
134       brcm,nand-oob-sector-size:
142           the flash geometry (particularly the NAND page
144           from NAND, the boot controller has only a limited
149       brcm,nand-ecc-use-strap:
152           settings from the SoC NAND boot strap configuration instead of
153           the generic NAND ECC settings. This is a common hardware design
154           on BCMBCA based boards. This strap ECC option and generic NAND
161   - $ref: nand-controller.yaml#
166             const: brcm,nand-bcm63138
171             - const: nand
172             - const: nand-int-base
177             const: brcm,nand-bcm6368
182             - const: nand
183             - const: nand-int-base
184             - const: nand-cache
189             const: brcm,nand-iproc
194             - const: nand
209         "^nand@[a-f0-9]$":
211             - brcm,nand-ecc-use-strap
214         "^nand@[a-f0-9]$":
216             nand-ecc-strength: false
217             nand-ecc-step-size: false
218             nand-ecc-maximize: false
219             nand-ecc-algo: false
220             brcm,nand-oob-sector-size: false
230     nand-controller@f0442800 {
234         reg-names = "nand", "flash-dma";
242         nand@1 {
245             nand-on-flash-bbt;
246             nand-ecc-strength = <12>;
247             nand-ecc-step-size = <512>;
254     nand-controller@10000200 {
255         compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",
260         reg-names = "nand", "nand-int-base", "nand-cache";
264         clock-names = "nand";
269         nand@0 {
272             nand-on-flash-bbt;
273             nand-ecc-strength = <1>;
274             nand-ecc-step-size = <512>;