Lines Matching +full:sd +full:- +full:uhs +full:- +full:ddr50
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
22 - ti,am64-sdhci-8bit
23 - ti,am654-sdhci-5.1
24 - ti,j721e-sdhci-4bit
25 - ti,j721e-sdhci-8bit
26 - items:
27 - const: ti,j7200-sdhci-8bit
28 - const: ti,j721e-sdhci-8bit
29 - items:
30 - const: ti,j7200-sdhci-4bit
31 - const: ti,j721e-sdhci-4bit
39 power-domains:
47 clock-names:
50 - const: clk_ahb
51 - const: clk_xin
53 dma-coherent:
61 ti,otap-del-sel-legacy:
62 description: Output tap delay for SD/MMC legacy timing
67 ti,otap-del-sel-mmc-hs:
73 ti,otap-del-sel-sd-hs:
74 description: Output tap delay for SD high speed timing
79 ti,otap-del-sel-sdr12:
80 description: Output tap delay for SD UHS SDR12 timing
85 ti,otap-del-sel-sdr25:
86 description: Output tap delay for SD UHS SDR25 timing
91 ti,otap-del-sel-sdr50:
92 description: Output tap delay for SD UHS SDR50 timing
97 ti,otap-del-sel-sdr104:
98 description: Output tap delay for SD UHS SDR104 timing
103 ti,otap-del-sel-ddr50:
104 description: Output tap delay for SD UHS DDR50 timing
109 ti,otap-del-sel-ddr52:
115 ti,otap-del-sel-hs200:
121 ti,otap-del-sel-hs400:
131 ti,itap-del-sel-legacy:
132 description: Input tap delay for SD/MMC legacy timing
137 ti,itap-del-sel-mmc-hs:
143 ti,itap-del-sel-sd-hs:
144 description: Input tap delay for SD high speed timing
149 ti,itap-del-sel-sdr12:
150 description: Input tap delay for SD UHS SDR12 timing
155 ti,itap-del-sel-sdr25:
156 description: Input tap delay for SD UHS SDR25 timing
161 ti,itap-del-sel-ddr50:
162 description: Input tap delay for MMC DDR50 timing
167 ti,itap-del-sel-ddr52:
173 ti,trm-icp:
179 ti,driver-strength-ohm:
183 - 33
184 - 40
185 - 50
186 - 66
187 - 100
189 ti,strobe-sel:
193 ti,clkbuf-sel:
197 ti,fails-without-test-cd:
205 - compatible
206 - reg
207 - interrupts
208 - clocks
209 - clock-names
210 - ti,otap-del-sel-legacy
215 - |
216 #include <dt-bindings/interrupt-controller/irq.h>
217 #include <dt-bindings/interrupt-controller/arm-gic.h>
220 #address-cells = <2>;
221 #size-cells = <2>;
224 compatible = "ti,am654-sdhci-5.1";
226 power-domains = <&k3_pds 47>;
228 clock-names = "clk_ahb", "clk_xin";
230 sdhci-caps-mask = <0x80000007 0x0>;
231 mmc-ddr-1_8v;
232 ti,otap-del-sel-legacy = <0x0>;
233 ti,otap-del-sel-mmc-hs = <0x0>;
234 ti,otap-del-sel-ddr52 = <0x5>;
235 ti,otap-del-sel-hs200 = <0x5>;
236 ti,otap-del-sel-hs400 = <0x0>;
237 ti,itap-del-sel-legacy = <0x10>;
238 ti,itap-del-sel-mmc-hs = <0xa>;
239 ti,itap-del-sel-ddr52 = <0x3>;
240 ti,trm-icp = <0x8>;