Lines Matching +full:dw +full:- +full:mshc +full:- +full:ciu +full:- +full:div
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Jaehoon Chung <jh80.chung@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - enum:
19 - axis,artpec8-dw-mshc
20 - samsung,exynos4210-dw-mshc
21 - samsung,exynos4412-dw-mshc
22 - samsung,exynos5250-dw-mshc
23 - samsung,exynos5420-dw-mshc
24 - samsung,exynos5420-dw-mshc-smu
25 - samsung,exynos7-dw-mshc
26 - samsung,exynos7-dw-mshc-smu
27 - samsung,exynos7870-dw-mshc
28 - samsung,exynos7870-dw-mshc-smu
29 - items:
30 - enum:
31 - samsung,exynos5433-dw-mshc-smu
32 - samsung,exynos7885-dw-mshc-smu
33 - samsung,exynos850-dw-mshc-smu
34 - samsung,exynos8895-dw-mshc-smu
35 - const: samsung,exynos7-dw-mshc-smu
46 Handle to "biu" and "ciu" clocks for the
49 clock-names:
51 - const: biu
52 - const: ciu
54 samsung,dw-mshc-ciu-div:
59 The divider value for the card interface unit (ciu) clock.
61 samsung,dw-mshc-ddr-timing:
62 $ref: /schemas/types.yaml#/definitions/uint32-array
64 - description: CIU clock phase shift value for tx mode
67 - description: CIU clock phase shift value for rx mode
71 The value of CUI clock phase shift value in transmit mode and CIU clock
73 See also samsung,dw-mshc-hs400-timing property.
75 samsung,dw-mshc-hs400-timing:
76 $ref: /schemas/types.yaml#/definitions/uint32-array
78 - description: CIU clock phase shift value for tx mode
81 - description: CIU clock phase shift value for rx mode
85 The value of CIU TX and RX clock phase shift value for HS400 mode
87 Valid values for SDR and DDR CIU clock timing::
88 - valid value for tx phase shift and rx phase shift is 0 to 7.
89 - when CIU clock divider value is set to 3, all possible 8 phase shift
91 - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
93 If missing, values from samsung,dw-mshc-ddr-timing property are used.
95 samsung,dw-mshc-sdr-timing:
96 $ref: /schemas/types.yaml#/definitions/uint32-array
98 - description: CIU clock phase shift value for tx mode
101 - description: CIU clock phase shift value for rx mode
105 The value of CIU clock phase shift value in transmit mode and CIU clock
107 See also samsung,dw-mshc-hs400-timing property.
109 samsung,read-strobe-delay:
116 - compatible
117 - reg
118 - interrupts
119 - clocks
120 - clock-names
121 - samsung,dw-mshc-ddr-timing
122 - samsung,dw-mshc-sdr-timing
125 - $ref: synopsys-dw-mshc-common.yaml#
126 - if:
131 - samsung,exynos5250-dw-mshc
132 - samsung,exynos5420-dw-mshc
133 - samsung,exynos7-dw-mshc
134 - samsung,exynos7-dw-mshc-smu
135 - axis,artpec8-dw-mshc
138 - samsung,dw-mshc-ciu-div
143 - |
144 #include <dt-bindings/clock/exynos5420.h>
145 #include <dt-bindings/interrupt-controller/arm-gic.h>
148 compatible = "samsung,exynos5420-dw-mshc";
150 #address-cells = <1>;
151 #size-cells = <0>;
154 clock-names = "biu", "ciu";
155 fifo-depth = <0x40>;
156 card-detect-delay = <200>;
157 samsung,dw-mshc-ciu-div = <3>;
158 samsung,dw-mshc-sdr-timing = <0 4>;
159 samsung,dw-mshc-ddr-timing = <0 2>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
162 bus-width = <4>;
163 cap-sd-highspeed;
164 max-frequency = <200000000>;
165 vmmc-supply = <&ldo19_reg>;
166 vqmmc-supply = <&ldo13_reg>;
167 sd-uhs-sdr50;
168 sd-uhs-sdr104;
169 sd-uhs-ddr50;