Lines Matching +full:clock +full:- +full:delay
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: sdhci-common.yaml#
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
25 - enum:
26 - fsl,imx25-esdhc
27 - fsl,imx35-esdhc
28 - fsl,imx51-esdhc
29 - fsl,imx53-esdhc
30 - fsl,imx6q-usdhc
31 - fsl,imx6sl-usdhc
32 - fsl,imx6sx-usdhc
33 - fsl,imx7d-usdhc
34 - fsl,imx7ulp-usdhc
35 - fsl,imx8mm-usdhc
36 - fsl,imxrt1050-usdhc
37 - nxp,s32g2-usdhc
38 - items:
39 - const: fsl,imx50-esdhc
40 - const: fsl,imx53-esdhc
41 - items:
42 - enum:
43 - fsl,imx6sll-usdhc
44 - fsl,imx6ull-usdhc
45 - fsl,imx6ul-usdhc
46 - const: fsl,imx6sx-usdhc
47 - items:
48 - const: fsl,imx7d-usdhc
49 - const: fsl,imx6sl-usdhc
50 - items:
51 - enum:
52 - fsl,imx8mq-usdhc
53 - const: fsl,imx7d-usdhc
54 - items:
55 - enum:
56 - fsl,imx8mn-usdhc
57 - fsl,imx8mp-usdhc
58 - fsl,imx8ulp-usdhc
59 - fsl,imx93-usdhc
60 - fsl,imx94-usdhc
61 - fsl,imx95-usdhc
62 - const: fsl,imx8mm-usdhc
63 - items:
64 - enum:
65 - fsl,imx8dxl-usdhc
66 - fsl,imx8qm-usdhc
67 - const: fsl,imx8qxp-usdhc
68 - items:
69 - enum:
70 - fsl,imx8mm-usdhc
71 - fsl,imx8mn-usdhc
72 - fsl,imx8mp-usdhc
73 - fsl,imx8qm-usdhc
74 - fsl,imx8qxp-usdhc
75 - const: fsl,imx7d-usdhc
77 - items:
78 - enum:
79 - fsl,imx8mn-usdhc
80 - fsl,imx8mp-usdhc
81 - const: fsl,imx8mm-usdhc
82 - const: fsl,imx7d-usdhc
84 - items:
85 - enum:
86 - fsl,imx8dxl-usdhc
87 - fsl,imx8qm-usdhc
88 - const: fsl,imx8qxp-usdhc
89 - const: fsl,imx7d-usdhc
91 - items:
92 - enum:
93 - fsl,imxrt1170-usdhc
94 - const: fsl,imxrt1050-usdhc
95 - items:
96 - const: nxp,s32g3-usdhc
97 - const: nxp,s32g2-usdhc
105 fsl,wp-controller:
110 fsl,delay-line:
113 Specify the number of delay cells for override mode.
114 This is used to set the clock delay for DLL(Delay Line) on override mode
115 to select a proper data sampling window in case the clock quality is not good
117 chapter, DLL (Delay Line) section in RM for details.
120 voltage-ranges:
121 $ref: /schemas/types.yaml#/definitions/uint32-matrix
129 - description: value for minimum slot voltage
130 - description: value for maximum slot voltage
133 fsl,tuning-start-tap:
136 Specify the start delay cell point when send first CMD19 in tuning procedure.
139 fsl,tuning-step:
142 Specify the increasing delay cell steps in tuning procedure.
143 The uSDHC use one delay cell as default increasing step to do tuning process.
144 This property allows user to change the tuning step to more than one delay
146 tuning step can't find the proper delay window within limited tuning retries.
149 fsl,strobe-dll-delay-target:
152 Specify the strobe dll control slave delay target.
153 This delay target programming host controller loopback read clock, and this
154 property allows user to change the delay target for the strobe input read clock.
155 If not use this property, driver default set the delay target to value 7.
164 clock-names:
166 - const: ipg
167 - const: ahb
168 - const: per
173 power-domains:
176 pinctrl-names:
178 - minItems: 3
180 - const: default
181 - const: state_100mhz
182 - const: state_200mhz
183 - const: sleep
184 - minItems: 2
186 - const: default
187 - const: state_100mhz
188 - const: sleep
189 - minItems: 1
191 - const: default
192 - const: sleep
195 - compatible
196 - reg
197 - interrupts
202 - |
204 compatible = "fsl,imx51-esdhc";
207 fsl,wp-controller;
211 compatible = "fsl,imx51-esdhc";
214 cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
215 wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */