Lines Matching +full:phy +full:- +full:input +full:- +full:delay +full:- +full:legacy
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - microchip,pic64gx-sd4hc
19 - mobileye,eyeq-sd4hc
20 - socionext,uniphier-sd4hc
21 - const: cdns,sd4hc
36 # PHY DLL input delays:
37 # They are used to delay the data valid window, and align the window to
38 # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
41 cdns,phy-input-delay-sd-highspeed:
42 description: Value of the delay in the input path for SD high-speed timing
47 cdns,phy-input-delay-legacy:
48 description: Value of the delay in the input path for legacy timing
53 cdns,phy-input-delay-sd-uhs-sdr12:
54 description: Value of the delay in the input path for SD UHS SDR12 timing
59 cdns,phy-input-delay-sd-uhs-sdr25:
60 description: Value of the delay in the input path for SD UHS SDR25 timing
65 cdns,phy-input-delay-sd-uhs-sdr50:
66 description: Value of the delay in the input path for SD UHS SDR50 timing
71 cdns,phy-input-delay-sd-uhs-ddr50:
72 description: Value of the delay in the input path for SD UHS DDR50 timing
77 cdns,phy-input-delay-mmc-highspeed:
78 description: Value of the delay in the input path for MMC high-speed timing
83 cdns,phy-input-delay-mmc-ddr:
84 description: Value of the delay in the input path for eMMC high-speed DDR timing
86 # PHY DLL clock delays:
87 # Each delay property represents the fraction of the clock period.
88 # The approximate delay value will be
89 # (<delay property value>/128)*sdmclk_clock_period.
94 cdns,phy-dll-delay-sdclk:
96 Value of the delay introduced on the sdclk output for all modes except
102 cdns,phy-dll-delay-sdclk-hsmmc:
104 Value of the delay introduced on the sdclk output for HS200, HS400 and
110 cdns,phy-dll-delay-strobe:
112 Value of the delay introduced on the dat_strobe input used in
119 - compatible
120 - reg
121 - interrupts
122 - clocks
125 - $ref: sdhci-common.yaml
126 - if:
130 const: amd,pensando-elba-sd4hc
135 - description: Host controller registers
136 - description: Elba byte-lane enable register for writes
138 - resets
147 - |
149 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
153 bus-width = <8>;
154 mmc-ddr-1_8v;
155 mmc-hs200-1_8v;
156 mmc-hs400-1_8v;
157 cdns,phy-dll-delay-sdclk = <0>;