Lines Matching full:delay

35   # They are used to delay the data valid window, and align the window to
36   # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
39   cdns,phy-input-delay-sd-highspeed:
40     description: Value of the delay in the input path for SD high-speed timing
45   cdns,phy-input-delay-legacy:
46     description: Value of the delay in the input path for legacy timing
51   cdns,phy-input-delay-sd-uhs-sdr12:
52     description: Value of the delay in the input path for SD UHS SDR12 timing
57   cdns,phy-input-delay-sd-uhs-sdr25:
58     description: Value of the delay in the input path for SD UHS SDR25 timing
63   cdns,phy-input-delay-sd-uhs-sdr50:
64     description: Value of the delay in the input path for SD UHS SDR50 timing
69   cdns,phy-input-delay-sd-uhs-ddr50:
70     description: Value of the delay in the input path for SD UHS DDR50 timing
75   cdns,phy-input-delay-mmc-highspeed:
76     description: Value of the delay in the input path for MMC high-speed timing
81   cdns,phy-input-delay-mmc-ddr:
82     description: Value of the delay in the input path for eMMC high-speed DDR timing
85   # Each delay property represents the fraction of the clock period.
86   # The approximate delay value will be
87   # (<delay property value>/128)*sdmclk_clock_period.
92   cdns,phy-dll-delay-sdclk:
94       Value of the delay introduced on the sdclk output for all modes except
100   cdns,phy-dll-delay-sdclk-hsmmc:
102       Value of the delay introduced on the sdclk output for HS200, HS400 and
108   cdns,phy-dll-delay-strobe:
110       Value of the delay introduced on the dat_strobe input used in
155         cdns,phy-dll-delay-sdclk = <0>;