Lines Matching +full:neg +full:- +full:edge
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Ulf Hansson <ulf.hansson@linaro.org>
20 - $ref: /schemas/arm/primecell.yaml#
21 - $ref: mmc-controller.yaml#
29 - arm,pl180
30 - arm,pl181
31 - arm,pl18x
33 - compatible
38 - description: The first version of the block, simply called
41 - const: arm,pl180
42 - const: arm,primecell
43 - description: The improved version of the block, found in the
48 - const: arm,pl181
49 - const: arm,primecell
50 - description: Wildcard entry that will let the operating system
54 - const: arm,pl18x
55 - const: arm,primecell
56 - description: Entries for STMicroelectronics variant of PL18x.
58 - enum:
59 - st,stm32-sdmmc2
60 - st,stm32mp25-sdmmc2
61 - const: arm,pl18x
62 - const: arm,primecell
73 dma-names:
75 - items:
76 - const: tx
77 - const: rx
78 - items:
79 - const: rx
80 - const: tx
82 access-controllers:
86 power-domains: true
103 only one interrupt may be provided. The interrupt-names property is
109 st,sig-dir-dat0:
111 description: ST Micro-specific property, bus signal direction pins used for
114 st,sig-dir-dat2:
116 description: ST Micro-specific property, bus signal direction pins used for
119 st,sig-dir-dat31:
121 description: ST Micro-specific property, bus signal direction pins used for
124 st,sig-dir-dat74:
126 description: ST Micro-specific property, bus signal direction pins used for
129 st,sig-dir-cmd:
131 description: ST Micro-specific property, CMD signal direction used for
134 st,sig-pin-fbclk:
136 description: ST Micro-specific property, feedback clock FBCLK signal pin
139 st,sig-dir:
141 description: ST Micro-specific property, signal direction polarity used for
144 st,neg-edge:
146 description: ST Micro-specific property, data and command phase relation,
147 generated on the sd clock falling edge.
149 st,use-ckin:
151 description: ST Micro-specific property, use CKIN pin from an external
155 st,cmd-gpios:
160 st,ck-gpios:
165 st,ckin-gpios:
171 st,cmd-gpios: [ "st,use-ckin" ]
172 st,ck-gpios: [ "st,use-ckin" ]
173 st,ckin-gpios: [ "st,use-ckin" ]
178 - compatible
179 - reg
180 - interrupts
183 - |
184 #include <dt-bindings/interrupt-controller/irq.h>
185 #include <dt-bindings/gpio/gpio.h>
190 interrupts-extended = <&vic 22 &sic 1>;
192 clock-names = "mclk", "apb_pclk";
195 - |
196 #include <dt-bindings/interrupt-controller/irq.h>
203 dma-names = "rx", "tx";
205 clock-names = "sdi", "apb_pclk";
206 max-frequency = <100000000>;
207 bus-width = <4>;
208 cap-sd-highspeed;
209 cap-mmc-highspeed;
210 cd-gpios = <&gpio2 31 0x4>;
211 st,sig-dir-dat0;
212 st,sig-dir-dat2;
213 st,sig-dir-cmd;
214 st,sig-pin-fbclk;
215 vmmc-supply = <&ab8500_ldo_aux3_reg>;
216 vqmmc-supply = <&vmmci>;
219 - |
224 clock-names = "mclk", "apb_pclk";
226 max-frequency = <400000>;
227 bus-width = <4>;
228 cap-mmc-highspeed;
229 cap-sd-highspeed;
230 full-pwr-cycle;
231 st,sig-dir-dat0;
232 st,sig-dir-dat2;
233 st,sig-dir-dat31;
234 st,sig-dir-cmd;
235 st,sig-pin-fbclk;
236 vmmc-supply = <&vmmc_regulator>;
239 - |
242 arm,primecell-periphid = <0x10153180>;
246 clock-names = "apb_pclk";
248 cap-sd-highspeed;
249 cap-mmc-highspeed;
250 max-frequency = <120000000>;