Lines Matching +full:phy +full:- +full:output +full:- +full:clock
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
28 - xlnx,zynqmp-8.9a
29 - xlnx,versal-8.9a
30 - xlnx,versal-net-emmc
33 clock-output-names:
35 - items:
36 - const: clk_out_sd0
37 - const: clk_in_sd0
38 - items:
39 - const: clk_out_sd1
40 - const: clk_in_sd1
41 - if:
45 const: renesas,rzn1-sdhci
54 - const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY
55 - const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY
56 - const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY
57 - items:
58 - const: renesas,r9a06g032-sdhci # Renesas RZ/N1D SoC
59 - const: renesas,rzn1-sdhci # Renesas RZ/N1 family
60 - const: arasan,sdhci-8.9a
61 - items:
62 - const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY
63 - const: arasan,sdhci-5.1
66 arasan,soc-ctl-syscon.
67 - items:
68 - const: xlnx,zynqmp-8.9a # ZynqMP SDHCI 8.9a PHY
69 - const: arasan,sdhci-8.9a
72 clock-output-names and '#clock-cells'.
73 - items:
74 - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
75 - const: arasan,sdhci-8.9a
78 clock-output-names and '#clock-cells'.
79 - const: xlnx,versal-net-emmc # Versal Net eMMC PHY
82 clock-output-names and '#clock-cells'.
83 - items:
84 - const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY
85 - const: arasan,sdhci-5.1
88 arasan,soc-ctl-syscon.
89 - items:
90 - const: intel,lgm-sdhci-5.1-sdxc # Intel LGM SDXC PHY
91 - const: arasan,sdhci-5.1
94 arasan,soc-ctl-syscon.
95 - items:
96 - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
97 - const: arasan,sdhci-5.1
100 arasan,soc-ctl-syscon.
101 - const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller
104 arasan,soc-ctl-syscon.
105 - const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO controller
108 arasan,soc-ctl-syscon.
117 clock-names:
120 - const: clk_xin
121 - const: clk_ahb
122 - const: gate
128 interrupt-names:
131 - const: int
132 - const: wakeup
137 phy-names:
143 arasan,soc-ctl-syscon:
150 clock-output-names:
154 Name of the card clock which will be exposed by this device.
156 '#clock-cells':
160 representing the Card Clock. These clocks are expected to be
161 consumed by our PHY.
163 xlnx,fails-without-test-cd:
170 xlnx,int-clock-stable-broken:
173 When present, the controller always reports that the internal clock
176 xlnx,mio-bank:
186 power-domains:
190 '#clock-cells': [ clock-output-names ]
193 - compatible
194 - reg
195 - interrupts
196 - clocks
197 - clock-names
202 - |
204 compatible = "arasan,sdhci-8.9a";
206 clock-names = "clk_xin", "clk_ahb";
208 interrupt-parent = <&gic>;
212 - |
214 compatible = "arasan,sdhci-5.1";
216 clock-names = "clk_xin", "clk_ahb";
218 interrupt-parent = <&gic>;
221 phy-names = "phy_arasan";
224 - |
225 #include <dt-bindings/clock/rk3399-cru.h>
226 #include <dt-bindings/interrupt-controller/arm-gic.h>
227 #include <dt-bindings/interrupt-controller/irq.h>
229 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
233 clock-names = "clk_xin", "clk_ahb";
234 arasan,soc-ctl-syscon = <&grf>;
235 assigned-clocks = <&cru SCLK_EMMC>;
236 assigned-clock-rates = <200000000>;
237 clock-output-names = "emmc_cardclock";
239 phy-names = "phy_arasan";
240 #clock-cells = <0>;
243 - |
245 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
246 interrupt-parent = <&gic>;
250 clock-names = "clk_xin", "clk_ahb", "gate";
251 clock-output-names = "clk_out_sd0", "clk_in_sd0";
252 #clock-cells = <1>;
253 clk-phase-sd-hs = <63>, <72>;
256 - |
258 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
259 interrupt-parent = <&gic>;
263 clock-names = "clk_xin", "clk_ahb", "gate";
264 clock-output-names = "clk_out_sd0", "clk_in_sd0";
265 #clock-cells = <1>;
266 clk-phase-sd-hs = <132>, <60>;
269 - |
274 compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
276 interrupt-parent = <&ioapic1>;
280 clock-names = "clk_xin", "clk_ahb", "gate";
281 clock-output-names = "emmc_cardclock";
282 #clock-cells = <0>;
284 phy-names = "phy_arasan";
285 arasan,soc-ctl-syscon = <&sysconf>;
288 - |
292 compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
294 interrupt-parent = <&ioapic1>;
298 clock-names = "clk_xin", "clk_ahb", "gate";
299 clock-output-names = "sdxc_cardclock";
300 #clock-cells = <0>;
302 phy-names = "phy_arasan";
303 arasan,soc-ctl-syscon = <&sysconf>;
306 - |
310 compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
313 clock-names = "clk_xin", "clk_ahb";
317 phy-names = "phy_arasan";
318 assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
319 assigned-clock-rates = <200000000>;
320 clock-output-names = "emmc_cardclock";
321 #clock-cells = <0>;
322 arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
325 - |
329 compatible = "intel,keembay-sdhci-5.1-sd";
332 clock-names = "clk_xin", "clk_ahb";
335 arasan,soc-ctl-syscon = <&sd0_phy_syscon>;