Lines Matching +full:mio +full:- +full:bank
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
28 - xlnx,zynqmp-8.9a
29 - xlnx,versal-8.9a
30 - xlnx,versal-net-emmc
33 clock-output-names:
35 - items:
36 - const: clk_out_sd0
37 - const: clk_in_sd0
38 - items:
39 - const: clk_out_sd1
40 - const: clk_in_sd1
45 - const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY
46 - const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY
47 - const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY
48 - items:
49 - const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY
50 - const: arasan,sdhci-5.1
53 arasan,soc-ctl-syscon.
54 - items:
55 - const: xlnx,zynqmp-8.9a # ZynqMP SDHCI 8.9a PHY
56 - const: arasan,sdhci-8.9a
59 clock-output-names and '#clock-cells'.
60 - items:
61 - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
62 - const: arasan,sdhci-8.9a
65 clock-output-names and '#clock-cells'.
66 - const: xlnx,versal-net-emmc # Versal Net eMMC PHY
69 clock-output-names and '#clock-cells'.
70 - items:
71 - const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY
72 - const: arasan,sdhci-5.1
75 arasan,soc-ctl-syscon.
76 - items:
77 - const: intel,lgm-sdhci-5.1-sdxc # Intel LGM SDXC PHY
78 - const: arasan,sdhci-5.1
81 arasan,soc-ctl-syscon.
82 - items:
83 - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
84 - const: arasan,sdhci-5.1
87 arasan,soc-ctl-syscon.
88 - const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller
91 arasan,soc-ctl-syscon.
92 - const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO controller
95 arasan,soc-ctl-syscon.
104 clock-names:
107 - const: clk_xin
108 - const: clk_ahb
109 - const: gate
117 phy-names:
123 arasan,soc-ctl-syscon:
130 clock-output-names:
136 '#clock-cells':
143 xlnx,fails-without-test-cd:
150 xlnx,int-clock-stable-broken:
156 xlnx,mio-bank:
161 The MIO bank number in which the command and data lines are configured.
166 power-domains:
170 '#clock-cells': [ clock-output-names ]
173 - compatible
174 - reg
175 - interrupts
176 - clocks
177 - clock-names
182 - |
184 compatible = "arasan,sdhci-8.9a";
186 clock-names = "clk_xin", "clk_ahb";
188 interrupt-parent = <&gic>;
192 - |
194 compatible = "arasan,sdhci-5.1";
196 clock-names = "clk_xin", "clk_ahb";
198 interrupt-parent = <&gic>;
201 phy-names = "phy_arasan";
204 - |
205 #include <dt-bindings/clock/rk3399-cru.h>
206 #include <dt-bindings/interrupt-controller/arm-gic.h>
207 #include <dt-bindings/interrupt-controller/irq.h>
209 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
213 clock-names = "clk_xin", "clk_ahb";
214 arasan,soc-ctl-syscon = <&grf>;
215 assigned-clocks = <&cru SCLK_EMMC>;
216 assigned-clock-rates = <200000000>;
217 clock-output-names = "emmc_cardclock";
219 phy-names = "phy_arasan";
220 #clock-cells = <0>;
223 - |
225 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
226 interrupt-parent = <&gic>;
230 clock-names = "clk_xin", "clk_ahb", "gate";
231 clock-output-names = "clk_out_sd0", "clk_in_sd0";
232 #clock-cells = <1>;
233 clk-phase-sd-hs = <63>, <72>;
236 - |
238 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
239 interrupt-parent = <&gic>;
243 clock-names = "clk_xin", "clk_ahb", "gate";
244 clock-output-names = "clk_out_sd0", "clk_in_sd0";
245 #clock-cells = <1>;
246 clk-phase-sd-hs = <132>, <60>;
249 - |
254 compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
256 interrupt-parent = <&ioapic1>;
260 clock-names = "clk_xin", "clk_ahb", "gate";
261 clock-output-names = "emmc_cardclock";
262 #clock-cells = <0>;
264 phy-names = "phy_arasan";
265 arasan,soc-ctl-syscon = <&sysconf>;
268 - |
272 compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
274 interrupt-parent = <&ioapic1>;
278 clock-names = "clk_xin", "clk_ahb", "gate";
279 clock-output-names = "sdxc_cardclock";
280 #clock-cells = <0>;
282 phy-names = "phy_arasan";
283 arasan,soc-ctl-syscon = <&sysconf>;
286 - |
290 compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
293 clock-names = "clk_xin", "clk_ahb";
297 phy-names = "phy_arasan";
298 assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
299 assigned-clock-rates = <200000000>;
300 clock-output-names = "emmc_cardclock";
301 #clock-cells = <0>;
302 arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
305 - |
309 compatible = "intel,keembay-sdhci-5.1-sd";
312 clock-names = "clk_xin", "clk_ahb";
315 arasan,soc-ctl-syscon = <&sd0_phy_syscon>;