Lines Matching +full:chip +full:- +full:select
3 The Octeon Boot Bus is a configurable parallel bus with 8 chip
4 selects. Each chip select is independently configurable.
7 - compatible: "cavium,octeon-3860-bootbus"
11 - reg: The base address of the Boot Bus' register bank.
13 - #address-cells: Must be <2>. The first cell is the chip select
14 within the bootbus. The second cell is the offset from the chip select.
16 - #size-cells: Must be <1>.
18 - ranges: There must be one one triplet of (child-bus-address,
19 parent-bus-address, length) for each active chip select. If the
20 length element for any triplet is zero, the chip select is disabled,
23 The configuration parameters for each chip select are stored in child
27 - compatible: "cavium,octeon-3860-bootbus-config"
29 - cavium,cs-index: A single cell indicating the chip select that
32 - cavium,t-adr: A cell specifying the ADR timing (in nS).
34 - cavium,t-ce: A cell specifying the CE timing (in nS).
36 - cavium,t-oe: A cell specifying the OE timing (in nS).
38 - cavium,t-we: A cell specifying the WE timing (in nS).
40 - cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).
42 - cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).
44 - cavium,t-pause: A cell specifying the PAUSE timing (in nS).
46 - cavium,t-wait: A cell specifying the WAIT timing (in nS).
48 - cavium,t-page: A cell specifying the PAGE timing (in nS).
50 - cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS).
52 - cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1
55 - cavium,wait-mode: Optional. If present, wait mode (WAITM) is selected.
57 - cavium,page-mode: Optional. If present, page mode (PAGEM) is selected.
59 - cavium,bus-width: A cell specifying the WIDTH parameter (in bits) of
60 the bus for this chip select.
62 - cavium,ale-mode: Optional. If present, ALE mode is selected.
64 - cavium,sam-mode: Optional. If present, SAM mode is selected.
66 - cavium,or-mode: Optional. If present, OR mode is selected.
70 compatible = "cavium,octeon-3860-bootbus";
72 /* The chip select number and offset */
73 #address-cells = <2>;
74 /* The size of the chip select region */
75 #size-cells = <1>;
85 cavium,cs-config@0 {
86 compatible = "cavium,octeon-3860-bootbus-config";
87 cavium,cs-index = <0>;
88 cavium,t-adr = <20>;
89 cavium,t-ce = <60>;
90 cavium,t-oe = <60>;
91 cavium,t-we = <45>;
92 cavium,t-rd-hld = <35>;
93 cavium,t-wr-hld = <45>;
94 cavium,t-pause = <0>;
95 cavium,t-wait = <0>;
96 cavium,t-page = <35>;
97 cavium,t-rd-dly = <0>;
100 cavium,bus-width = <8>;
105 cavium,cs-config@6 {
106 compatible = "cavium,octeon-3860-bootbus-config";
107 cavium,cs-index = <6>;
108 cavium,t-adr = <5>;
109 cavium,t-ce = <300>;
110 cavium,t-oe = <270>;
111 cavium,t-we = <150>;
112 cavium,t-rd-hld = <100>;
113 cavium,t-wr-hld = <70>;
114 cavium,t-pause = <0>;
115 cavium,t-wait = <0>;
116 cavium,t-page = <320>;
117 cavium,t-rd-dly = <0>;
120 cavium,wait-mode;
121 cavium,bus-width = <16>;