Lines Matching +full:bcm6328 +full:- +full:power +full:- +full:controller
5 - compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843"
6 "brcm,bcm3384-viper", "brcm,bcm33843-viper"
7 "brcm,bcm6328", "brcm,bcm6358", "brcm,bcm6362", "brcm,bcm6368",
12 The experimental -viper variants are for running Linux on the 3384's
15 Power management
16 ----------------
18 For power management (particularly, S2/S3/S5 system suspend), the following SoC
21 = Always-On control block (AON CTRL)
23 This hardware provides control registers for the "always-on" (even in low-power
24 modes) hardware, such as the Power Management State Machine (PMSM).
27 - compatible : should be one of
28 "brcm,bcm7425-aon-ctrl"
29 "brcm,bcm7429-aon-ctrl"
30 "brcm,bcm7435-aon-ctrl" and
31 "brcm,brcmstb-aon-ctrl"
32 - reg : the register start and length for the AON CTRL block
37 compatible = "brcm,bcm7425-aon-ctrl", "brcm,brcmstb-aon-ctrl";
47 contains N sub-nodes (one for each controller in the system), each of which is
50 == MEMC (MEMory Controller)
52 Represents a single memory controller instance.
55 - compatible : should contain "brcm,brcmstb-memc" and "simple-bus"
56 - ranges : should contain the child address in the parent address
58 the entire memory controller (including all sub nodes: DDR PHY,
60 - #address-cells : must be 1
61 - #size-cells : must be 1
65 memory-controller@0 {
66 compatible = "brcm,brcmstb-memc", "simple-bus";
68 #address-cells = <1>;
69 #size-cells = <1>;
71 memc-arb@1000 {
75 memc-ddr@2000 {
79 ddr-phy@6000 {
88 Control registers for this memory controller's DDR PHY.
91 - compatible : should contain one of these
92 "brcm,brcmstb-ddr-phy-v64.5"
93 "brcm,brcmstb-ddr-phy"
95 - reg : the DDR PHY register range and length
99 ddr-phy@6000 {
100 compatible = "brcm,brcmstb-ddr-phy-v64.5";
104 == DDR memory controller sequencer
106 Control registers for this memory controller's DDR memory sequencer
109 - compatible : should contain one of these
110 "brcm,bcm7425-memc-ddr"
111 "brcm,bcm7429-memc-ddr"
112 "brcm,bcm7435-memc-ddr" and
113 "brcm,brcmstb-memc-ddr"
115 - reg : the DDR sequencer register range and length
119 memc-ddr@2000 {
120 compatible = "brcm,bcm7425-memc-ddr", "brcm,brcmstb-memc-ddr";
126 The memory controller arbiter is responsible for memory clients allocation
132 - compatible : should contain one of these
133 "brcm,brcmstb-memc-arb-v10.0.0.0"
134 "brcm,brcmstb-memc-arb"
136 - reg : the DDR Arbiter register range and length
140 memc-arb@1000 {
141 compatible = "brcm,brcmstb-memc-arb-v10.0.0.0";
152 - compatible : should contain one of:
153 "brcm,bcm7425-timers"
154 "brcm,bcm7429-timers"
155 "brcm,bcm7435-timers" and
156 "brcm,brcmstb-timers"
157 - reg : the timers register range
158 - interrupts : the interrupt line for this timer block
163 compatible = "brcm,bcm7425-timers", "brcm,brcmstb-timers";