Lines Matching +full:ocelot +full:- +full:miim
1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
3 ---
4 $id: http://devicetree.org/schemas/mfd/mscc,ocelot.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ocelot Externally-Controlled Ethernet Switch
10 - Colin Foster <colin.foster@in-advantage.com>
13 The Ocelot ethernet switch family contains chips that have an internal CPU
18 The switch family is a multi-port networking switch that supports many
25 - mscc,vsc7512
30 "#address-cells":
33 "#size-cells":
36 spi-max-frequency:
40 "^pinctrl@[0-9a-f]+$":
42 $ref: /schemas/pinctrl/mscc,ocelot-pinctrl.yaml
44 "^gpio@[0-9a-f]+$":
46 $ref: /schemas/pinctrl/microchip,sparx5-sgpio.yaml
50 - mscc,ocelot-sgpio
52 "^mdio@[0-9a-f]+$":
54 $ref: /schemas/net/mscc,miim.yaml
58 - mscc,ocelot-miim
60 "^ethernet-switch@[0-9a-f]+$":
62 $ref: /schemas/net/mscc,vsc7514-switch.yaml
67 - mscc,vsc7512-switch
70 - compatible
71 - reg
72 - '#address-cells'
73 - '#size-cells'
78 - |
80 #address-cells = <1>;
81 #size-cells = <0>;
85 spi-max-frequency = <2500000>;
87 #address-cells = <1>;
88 #size-cells = <1>;
91 compatible = "mscc,ocelot-miim";
92 #address-cells = <1>;
93 #size-cells = <0>;
96 sw_phy0: ethernet-phy@0 {
102 compatible = "mscc,ocelot-miim";
103 pinctrl-names = "default";
104 pinctrl-0 = <&miim1_pins>;
105 #address-cells = <1>;
106 #size-cells = <0>;
109 sw_phy4: ethernet-phy@4 {
115 compatible = "mscc,ocelot-pinctrl";
116 gpio-controller;
117 #gpio-cells = <2>;
118 gpio-ranges = <&gpio 0 0 22>;
121 sgpio_pins: sgpio-pins {
126 miim1_pins: miim1-pins {
128 function = "miim";
133 compatible = "mscc,ocelot-sgpio";
134 #address-cells = <1>;
135 #size-cells = <0>;
136 bus-frequency = <12500000>;
138 microchip,sgpio-port-ranges = <0 15>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&sgpio_pins>;
144 compatible = "microchip,sparx5-sgpio-bank";
146 gpio-controller;
147 #gpio-cells = <3>;
152 compatible = "microchip,sparx5-sgpio-bank";
154 gpio-controller;
155 #gpio-cells = <3>;