Lines Matching +full:lpc +full:- +full:interrupts
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Aspeed Low Pin Count (LPC) Bus Controller
11 - Andrew Jeffery <andrew@aj.id.au>
12 - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
15 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
17 primary use case of the Aspeed LPC controller is as a slave on the bus
21 The LPC controller is represented as a multi-function device to account for the
26 * An LPC Host Interface Controller manages functions exposed to the host such
27 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
34 Additionally the state of the LPC controller influences the pinmux
41 - enum:
42 - aspeed,ast2400-lpc-v2
43 - aspeed,ast2500-lpc-v2
44 - aspeed,ast2600-lpc-v2
45 - const: simple-mfd
46 - const: syscon
51 "#address-cells":
54 "#size-cells":
60 "^lpc-ctrl@[0-9a-f]+$":
65 The LPC Host Interface Controller manages functions exposed to the host such as
66 LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management
72 - enum:
73 - aspeed,ast2400-lpc-ctrl
74 - aspeed,ast2500-lpc-ctrl
75 - aspeed,ast2600-lpc-ctrl
83 memory-region:
85 description: handle to memory reservation for the LPC to AHB mapping region
89 …description: The SPI flash controller containing the flash to be exposed over the LPC to AHB mappi…
92 - compatible
93 - clocks
95 "^reset-controller@[0-9a-f]+$":
101 state of the LPC bus. Some systems may chose to modify this configuration
106 - enum:
107 - aspeed,ast2400-lpc-reset
108 - aspeed,ast2500-lpc-reset
109 - aspeed,ast2600-lpc-reset
114 '#reset-cells':
118 - compatible
119 - '#reset-cells'
121 "^lpc-snoop@[0-9a-f]+$":
126 The LPC snoop interface allows the BMC to listen on and record the data
127 bytes written by the Host to the targeted LPC I/O pots.
132 - enum:
133 - aspeed,ast2400-lpc-snoop
134 - aspeed,ast2500-lpc-snoop
135 - aspeed,ast2600-lpc-snoop
140 interrupts:
143 snoop-ports:
144 $ref: /schemas/types.yaml#/definitions/uint32-array
145 description: The LPC I/O ports to snoop
148 - compatible
149 - interrupts
150 - snoop-ports
152 "^uart-routing@[0-9a-f]+$":
153 $ref: /schemas/soc/aspeed/uart-routing.yaml#
154 description: The UART routing control under LPC register space
157 - compatible
158 - reg
159 - "#address-cells"
160 - "#size-cells"
161 - ranges
167 - |
168 #include <dt-bindings/interrupt-controller/arm-gic.h>
169 #include <dt-bindings/clock/ast2600-clock.h>
171 lpc: lpc@1e789000 {
172 compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
175 #address-cells = <1>;
176 #size-cells = <1>;
179 lpc_ctrl: lpc-ctrl@80 {
180 compatible = "aspeed,ast2600-lpc-ctrl";
183 memory-region = <&flash_memory>;
187 lpc_reset: reset-controller@98 {
188 compatible = "aspeed,ast2600-lpc-reset";
190 #reset-cells = <1>;
193 lpc_snoop: lpc-snoop@90 {
194 compatible = "aspeed,ast2600-lpc-snoop";
196 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
197 snoop-ports = <0x80>;