Lines Matching +full:chip +full:- +full:select
4 provide a glue-less interface to a variety of asynchronous memory devices like
6 can be accessed at any given time via four chip selects with 64M byte access
7 per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
26 (N - total number of partitions). It's recommended to
27 assign N-1 number for the control partition. The second
30 - #size-cells: Must be set to 1.
32 - ranges: Contains memory regions. There are two types of
34 - CS-specific partition/range. If continuous, must be
37 child device can select the proper one.
38 - control partition which is common for all CS
41 - clocks: the clock feeding the controller clock. Required only
43 See clock-bindings.txt
45 - clock-names: clock name. It has to be "aemif". Required only if clock
48 See clock-bindings.txt
50 - clock-ranges: Empty property indicating that child nodes can inherit
53 See clock-bindings.txt
56 Child chip-select (cs) nodes contain the memory devices nodes connected to
57 such as NOR (e.g. cfi-flash) and NAND (ti,davinci-nand, see davinci-nand.txt).
62 - #address-cells: Must be 2.
64 - #size-cells: Must be 1.
66 - ranges: Empty property indicating that child nodes can inherit
69 - clock-ranges: Empty property indicating that child nodes can inherit
73 - ti,cs-chipselect: number of chipselect. Indicates on the aemif driver
75 compatibles "ti,davinci-aemif" and "ti,keystone-aemif"
76 it can be in range [0-3]. For compatible
77 "ti,da850-aemif" range is [2-5].
81 - ti,cs-bus-width: width of the asynchronous device's data bus
84 - ti,cs-select-strobe-mode: enable/disable select strobe mode
85 In select strobe mode chip select behaves as
89 - ti,cs-extended-wait-mode: enable/disable extended wait mode
91 mapped to that chip select to determine if the
95 - ti,cs-min-turnaround-ns: minimum turn around time, ns
100 followed by a write to same chip select.
102 - ti,cs-read-setup-ns: read setup width, ns
107 - ti,cs-read-strobe-ns: read strobe width, ns
112 - ti,cs-read-hold-ns: read hold width, ns
116 the chip select signal.
119 - ti,cs-write-setup-ns: write setup width, ns
124 - ti,cs-write-strobe-ns: write strobe width, ns
129 - ti,cs-write-hold-ns: write hold width, ns
133 the chip select signal.
139 Example for aemif, davinci nand and nor flash chip select shown below.
141 memory-controller@21000a00 {
142 compatible = "ti,davinci-aemif";
143 #address-cells = <2>;
144 #size-cells = <1>;
146 clock-names = "aemif";
147 clock-ranges;
152 * Partition0: CS-specific memory range which is
158 #address-cells = <2>;
159 #size-cells = <1>;
160 clock-ranges;
163 ti,cs-chipselect = <2>;
165 ti,cs-min-turnaround-ns = <0>;
166 ti,cs-read-hold-ns = <7>;
167 ti,cs-read-strobe-ns = <42>;
168 ti,cs-read-setup-ns = <14>;
169 ti,cs-write-hold-ns = <7>;
170 ti,cs-write-strobe-ns = <42>;
171 ti,cs-write-setup-ns = <14>;
174 compatible = "ti,davinci-nand";
182 .. see davinci-nand.txt
187 #address-cells = <2>;
188 #size-cells = <1>;
189 clock-ranges;
192 ti,cs-chipselect = <0>;
194 ti,cs-min-turnaround-ns = <0>;
195 ti,cs-read-hold-ns = <8>;
196 ti,cs-read-strobe-ns = <40>;
197 ti,cs-read-setup-ns = <14>;
198 ti,cs-write-hold-ns = <7>;
199 ti,cs-write-strobe-ns = <40>;
200 ti,cs-write-setup-ns = <14>;
201 ti,cs-bus-width = <16>;
204 compatible = "cfi-flash";