Lines Matching +full:wait +full:- +full:pin
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
16 - Asynchronous SRAM-like memories and ASICs
17 - Asynchronous, synchronous, and page mode burst NOR flash
18 - NAND flash
19 - Pseudo-SRAM devices
24 - enum:
25 - ti,am3352-gpmc
26 - ti,am64-gpmc
27 - ti,omap2420-gpmc
28 - ti,omap2430-gpmc
29 - ti,omap3430-gpmc
30 - ti,omap4430-gpmc
36 reg-names:
38 - const: cfg
39 - const: data
50 clock-names:
52 - const: fck
54 power-domains:
59 - description: DMA channel for GPMC NAND prefetch
61 dma-names:
63 - const: rxtx
65 "#address-cells": true
67 "#size-cells": true
69 gpmc,num-cs:
70 description: maximum number of supported chip-select lines.
73 gpmc,num-waitpins:
74 description: maximum number of supported wait pins.
81 integer values for each chip-select line in use,
82 <cs-number> 0 <physical address of mapping> <size>
84 - description: NAND bank 0
85 - description: NOR/SRAM bank 0
86 - description: NOR/SRAM bank 1
88 '#interrupt-cells':
91 interrupt-controller:
97 0 - NAND_fifoevent
98 1 - NAND_termcount
99 2 - GPMC_WAIT0 pin edge
100 3 - GPMC_WAIT1 pin edge, and so on.
102 '#gpio-cells':
105 gpio-controller:
108 GPMC WAIT pins that can be used as general purpose inputs.
109 0 maps to GPMC_WAIT0 pin.
118 ti,no-idle-on-init:
126 "@[0-7],[a-f0-9]+$":
132 $ref: ti,gpmc-child.yaml
136 - compatible
137 - reg
138 - gpmc,num-cs
139 - gpmc,num-waitpins
140 - "#address-cells"
141 - "#size-cells"
144 - if:
148 const: ti,am64-gpmc
151 - reg-names
152 - power-domains
157 - |
158 #include <dt-bindings/interrupt-controller/arm-gic.h>
159 #include <dt-bindings/gpio/gpio.h>
161 gpmc: memory-controller@50000000 {
162 compatible = "ti,am3352-gpmc";
166 clock-names = "fck";
168 dma-names = "rxtx";
169 gpmc,num-cs = <8>;
170 gpmc,num-waitpins = <2>;
171 #address-cells = <2>;
172 #size-cells = <1>;
174 interrupt-controller;
175 #interrupt-cells = <2>;
176 gpio-controller;
177 #gpio-cells = <2>;
180 compatible = "ti,omap2-nand";
182 interrupt-parent = <&gpmc>;
185 ti,nand-xfer-type = "prefetch-dma";
186 ti,nand-ecc-opt = "bch16";
187 ti,elm-id = <&elm>;
188 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */