Lines Matching +full:default +full:- +full:mode
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
23 # GPMC Timing properties for child nodes. All are optional and default to 0.
24 gpmc,sync-clk-ps:
25 description: Minimum clock period for synchronous mode
26 default: 0
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
31 default: 0
33 gpmc,cs-rd-off-ns:
35 default: 0
37 gpmc,cs-wr-off-ns:
39 default: 0
42 gpmc,adv-on-ns:
44 default: 0
46 gpmc,adv-rd-off-ns:
48 default: 0
50 gpmc,adv-wr-off-ns:
52 default: 0
54 gpmc,adv-aad-mux-on-ns:
56 default: 0
58 gpmc,adv-aad-mux-rd-off-ns:
60 default: 0
62 gpmc,adv-aad-mux-wr-off-ns:
64 default: 0
67 gpmc,we-on-ns:
69 default: 0
71 gpmc,we-off-ns:
73 default: 0
76 gpmc,oe-on-ns:
78 default: 0
80 gpmc,oe-off-ns:
82 default: 0
84 gpmc,oe-aad-mux-on-ns:
86 default: 0
88 gpmc,oe-aad-mux-off-ns:
90 default: 0
94 gpmc,page-burst-access-ns:
96 default: 0
98 gpmc,access-ns:
99 description: Start-cycle to first data valid delay
100 default: 0
102 gpmc,rd-cycle-ns:
104 default: 0
106 gpmc,wr-cycle-ns:
108 default: 0
110 gpmc,bus-turnaround-ns:
111 description: Turn-around time between successive accesses
112 default: 0
114 gpmc,cycle2cycle-delay-ns:
115 description: Delay between chip-select pulses
116 default: 0
118 gpmc,clk-activation-ns:
120 default: 0
122 gpmc,wait-monitoring-ns:
124 default: 0
128 gpmc,adv-extra-delay:
132 gpmc,cs-extra-delay:
136 gpmc,cycle2cycle-diffcsen:
138 Add "cycle2cycle-delay" between successive accesses
142 gpmc,cycle2cycle-samecsen:
144 Add "cycle2cycle-delay" between successive accesses
148 gpmc,oe-extra-delay:
152 gpmc,we-extra-delay:
156 gpmc,time-para-granularity:
161 gpmc,wr-access-ns:
163 In synchronous write mode, for single or
168 default: 0
170 gpmc,wr-data-mux-bus-ns:
172 In address-data multiplex mode, specifies
174 the address-data bus.
175 default: 0
177 # GPMC chip-select settings properties for child nodes. All are optional.
178 gpmc,burst-length:
182 default: 0
184 gpmc,burst-wrap:
188 gpmc,burst-read:
189 description: Enables read page/burst mode
192 gpmc,burst-write:
193 description: Enables write page/burst mode
196 gpmc,device-width:
199 chip-select in bytes. The GPMC supports 8-bit
200 and 16-bit devices and so this property must be
204 default: 1
206 gpmc,mux-add-data:
210 0 for Non multiplexed mode
211 1 for address-address-data multiplexing mode and
212 2 for address-data multiplexing mode.
216 gpmc,sync-read:
222 gpmc,sync-write:
228 gpmc,wait-pin:
230 Wait-pin used by client. Must be less than "gpmc,num-waitpins".
233 ti,wait-pin-polarity:
240 gpmc,wait-on-read:
244 gpmc,wait-on-write:
249 - reg