Lines Matching +full:exynos5422 +full:- +full:dmc
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory
12 - Krzysztof Kozlowski <krzk@kernel.org>
13 - Lukasz Luba <lukasz.luba@arm.com>
16 The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
22 switch the DMC and memory frequency.
27 - const: samsung,exynos5422-dmc
29 clock-names:
31 - const: fout_spll
32 - const: mout_sclk_spll
33 - const: ff_dout_spll2
34 - const: fout_bpll
35 - const: mout_bpll
36 - const: sclk_bpll
37 - const: mout_mx_mspll_ccore
38 - const: mout_mclk_cdrex
44 devfreq-events:
45 $ref: /schemas/types.yaml#/definitions/phandle-array
52 device-handle:
58 operating-points-v2: true
62 - description: DMC internal performance event counters in DREX0
63 - description: DMC internal performance event counters in DREX1
65 interrupt-names:
67 - const: drex_0
68 - const: drex_1
72 - description: registers of DREX0
73 - description: registers of DREX1
75 samsung,syscon-clk:
83 vdd-supply: true
86 - compatible
87 - clock-names
88 - clocks
89 - devfreq-events
90 - device-handle
91 - reg
92 - samsung,syscon-clk
97 - |
98 #include <dt-bindings/clock/exynos5420.h>
100 compatible = "samsung,exynos-ppmu";
103 clock-names = "ppmu";
105 ppmu_event_dmc0_0: ppmu-event3-dmc0-0 {
106 event-name = "ppmu-event3-dmc0_0";
111 memory-controller@10c20000 {
112 compatible = "samsung,exynos5422-dmc";
122 clock-names = "fout_spll",
130 operating-points-v2 = <&dmc_opp_table>;
131 devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
133 device-handle = <&samsung_K3QF2F20DB>;
134 vdd-supply = <&buck1_reg>;
135 samsung,syscon-clk = <&clock>;
136 interrupt-parent = <&combiner>;
138 interrupt-names = "drex_0", "drex_1";