Lines Matching +full:emc +full:- +full:configuration
1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
22 const: nvidia,tegra124-mc
30 clock-names:
32 - const: mc
37 "#reset-cells":
40 "#iommu-cells":
43 "#interconnect-cells":
47 "^emc-timings-[0-9]+$":
50 nvidia,ram-code:
56 "^timing-[0-9]+$":
59 clock-frequency:
65 nvidia,emem-configuration:
66 $ref: /schemas/types.yaml#/definitions/uint32-array
71 - description: MC_EMEM_ARB_CFG
72 - description: MC_EMEM_ARB_OUTSTANDING_REQ
73 - description: MC_EMEM_ARB_TIMING_RCD
74 - description: MC_EMEM_ARB_TIMING_RP
75 - description: MC_EMEM_ARB_TIMING_RC
76 - description: MC_EMEM_ARB_TIMING_RAS
77 - description: MC_EMEM_ARB_TIMING_FAW
78 - description: MC_EMEM_ARB_TIMING_RRD
79 - description: MC_EMEM_ARB_TIMING_RAP2PRE
80 - description: MC_EMEM_ARB_TIMING_WAP2PRE
81 - description: MC_EMEM_ARB_TIMING_R2R
82 - description: MC_EMEM_ARB_TIMING_W2W
83 - description: MC_EMEM_ARB_TIMING_R2W
84 - description: MC_EMEM_ARB_TIMING_W2R
85 - description: MC_EMEM_ARB_DA_TURNS
86 - description: MC_EMEM_ARB_DA_COVERS
87 - description: MC_EMEM_ARB_MISC0
88 - description: MC_EMEM_ARB_MISC1
89 - description: MC_EMEM_ARB_RING1_THROTTLE
92 - clock-frequency
93 - nvidia,emem-configuration
98 - nvidia,ram-code
103 - compatible
104 - reg
105 - interrupts
106 - clocks
107 - clock-names
108 - "#reset-cells"
109 - "#iommu-cells"
110 - "#interconnect-cells"
115 - |
116 memory-controller@70019000 {
117 compatible = "nvidia,tegra124-mc";
120 clock-names = "mc";
124 #iommu-cells = <1>;
125 #reset-cells = <1>;
126 #interconnect-cells = <1>;
128 emc-timings-3 {
129 nvidia,ram-code = <3>;
131 timing-12750000 {
132 clock-frequency = <12750000>;
134 nvidia,emem-configuration = <