Lines Matching +full:ixp43x +full:- +full:interrupt
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
12 including IXP42x, IXP43x, IXP45x and IXP46x.
15 - Linus Walleij <linus.walleij@linaro.org>
19 pattern: '^bus@[0-9a-f]+$'
23 - enum:
24 - intel,ixp42x-expansion-bus-controller
25 - intel,ixp43x-expansion-bus-controller
26 - intel,ixp45x-expansion-bus-controller
27 - intel,ixp46x-expansion-bus-controller
28 - const: syscon
35 native-endian:
39 the SoC is running in big-endian or little-endian mode. Thus the
42 "#address-cells":
48 "#size-cells":
52 dma-ranges: true
55 "^.*@[0-7],[0-9a-f]+$":
59 $ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
63 - compatible
64 - reg
65 - native-endian
66 - "#address-cells"
67 - "#size-cells"
68 - ranges
69 - dma-ranges
74 - |
75 #include <dt-bindings/interrupt-controller/irq.h>
77 compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
79 native-endian;
80 #address-cells = <2>;
81 #size-cells = <1>;
84 dma-ranges = <0 0x0 0x50000000 0x01000000>,
87 compatible = "intel,ixp4xx-flash", "cfi-flash";
88 bank-width = <2>;
90 intel,ixp4xx-eb-t3 = <3>;
91 intel,ixp4xx-eb-cycle-type = <0>;
92 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
93 intel,ixp4xx-eb-write-enable = <1>;
94 intel,ixp4xx-eb-byte-access = <0>;
99 interrupt-parent = <&gpio0>;
101 clock-frequency = <1843200>;
102 intel,ixp4xx-eb-t3 = <3>;
103 intel,ixp4xx-eb-cycle-type = <1>;
104 intel,ixp4xx-eb-write-enable = <1>;
105 intel,ixp4xx-eb-byte-access = <1>;