Lines Matching +full:clock +full:- +full:lanes
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/qcom,sm8250-camss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Robert Foss <robert.foss@linaro.org>
18 const: qcom,sm8250-camss
24 clock-names:
26 - const: cam_ahb_clk
27 - const: cam_hf_axi
28 - const: cam_sf_axi
29 - const: camnoc_axi
30 - const: camnoc_axi_src
31 - const: core_ahb
32 - const: cpas_ahb
33 - const: csiphy0
34 - const: csiphy0_timer
35 - const: csiphy1
36 - const: csiphy1_timer
37 - const: csiphy2
38 - const: csiphy2_timer
39 - const: csiphy3
40 - const: csiphy3_timer
41 - const: csiphy4
42 - const: csiphy4_timer
43 - const: csiphy5
44 - const: csiphy5_timer
45 - const: slow_ahb_src
46 - const: vfe0_ahb
47 - const: vfe0_axi
48 - const: vfe0
49 - const: vfe0_cphy_rx
50 - const: vfe0_csid
51 - const: vfe0_areg
52 - const: vfe1_ahb
53 - const: vfe1_axi
54 - const: vfe1
55 - const: vfe1_cphy_rx
56 - const: vfe1_csid
57 - const: vfe1_areg
58 - const: vfe_lite_ahb
59 - const: vfe_lite_axi
60 - const: vfe_lite
61 - const: vfe_lite_cphy_rx
62 - const: vfe_lite_csid
68 interrupt-names:
70 - const: csiphy0
71 - const: csiphy1
72 - const: csiphy2
73 - const: csiphy3
74 - const: csiphy4
75 - const: csiphy5
76 - const: csid0
77 - const: csid1
78 - const: csid2
79 - const: csid3
80 - const: vfe0
81 - const: vfe1
82 - const: vfe_lite0
83 - const: vfe_lite1
93 interconnect-names:
95 - const: cam_ahb
96 - const: cam_hf_0_mnoc
97 - const: cam_sf_0_mnoc
98 - const: cam_sf_icp_mnoc
100 power-domains:
102 - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
103 - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
104 - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
114 $ref: /schemas/graph.yaml#/$defs/port-base
121 $ref: video-interfaces.yaml#
125 clock-lanes:
128 data-lanes:
133 - clock-lanes
134 - data-lanes
137 $ref: /schemas/graph.yaml#/$defs/port-base
144 $ref: video-interfaces.yaml#
148 clock-lanes:
151 data-lanes:
156 - clock-lanes
157 - data-lanes
160 $ref: /schemas/graph.yaml#/$defs/port-base
167 $ref: video-interfaces.yaml#
171 clock-lanes:
174 data-lanes:
179 - clock-lanes
180 - data-lanes
183 $ref: /schemas/graph.yaml#/$defs/port-base
190 $ref: video-interfaces.yaml#
194 clock-lanes:
197 data-lanes:
202 - clock-lanes
203 - data-lanes
206 $ref: /schemas/graph.yaml#/$defs/port-base
213 $ref: video-interfaces.yaml#
217 clock-lanes:
220 data-lanes:
225 - clock-lanes
226 - data-lanes
229 $ref: /schemas/graph.yaml#/$defs/port-base
236 $ref: video-interfaces.yaml#
240 clock-lanes:
243 data-lanes:
248 - clock-lanes
249 - data-lanes
255 reg-names:
257 - const: csiphy0
258 - const: csiphy1
259 - const: csiphy2
260 - const: csiphy3
261 - const: csiphy4
262 - const: csiphy5
263 - const: vfe0
264 - const: vfe1
265 - const: vfe_lite0
266 - const: vfe_lite1
268 vdda-phy-supply:
272 vdda-pll-supply:
277 - clock-names
278 - clocks
279 - compatible
280 - interconnects
281 - interconnect-names
282 - interrupts
283 - interrupt-names
284 - iommus
285 - power-domains
286 - reg
287 - reg-names
288 - vdda-phy-supply
289 - vdda-pll-supply
294 - |
295 #include <dt-bindings/interrupt-controller/arm-gic.h>
296 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
297 #include <dt-bindings/interconnect/qcom,sm8250.h>
298 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
299 #include <dt-bindings/power/qcom-rpmpd.h>
302 #address-cells = <2>;
303 #size-cells = <2>;
306 compatible = "qcom,sm8250-camss";
318 reg-names = "csiphy0",
329 vdda-phy-supply = <&vreg_l5a_0p88>;
330 vdda-pll-supply = <&vreg_l9a_1p2>;
346 interrupt-names = "csiphy0",
361 power-domains = <&camcc IFE_0_GDSC>,
402 clock-names = "cam_ahb_clk",
453 interconnect-names = "cam_ahb",
459 #address-cells = <1>;
460 #size-cells = <0>;