Lines Matching +full:phy +full:- +full:ref +full:- +full:clk
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MQ MIPI CSI-2 receiver
10 - Martin Kepplinger <martin.kepplinger@puri.sm>
12 description: |-
13 This binding covers the CSI-2 RX PHY and host controller included in the
20 - enum:
21 - fsl,imx8mq-mipi-csi2
22 - fsl,imx8qxp-mipi-csi2
23 - items:
24 - const: fsl,imx8qm-mipi-csi2
25 - const: fsl,imx8qxp-mipi-csi2
29 - description: MIPI CSI-2 RX host controller register.
30 - description: MIPI CSI-2 control and status register (csr).
35 - description: core is the RX Controller Core Clock input. This clock
38 - description: esc is the Rx Escape Clock. This must be the same escape
40 - description: ui is the pixel clock (phy_ref up to 333Mhz).
43 clock-names:
45 - const: core
46 - const: esc
47 - const: ui
49 power-domains:
54 - description: CORE_RESET reset register bit definition
55 - description: PHY_REF_RESET reset register bit definition
56 - description: ESC_RESET reset register bit definition
59 fsl,mipi-phy-gpr:
61 The phandle to the imx8mq syscon iomux-gpr with the register
67 req_gpr is the gpr register offset of RX_ENABLE for the mipi phy.
68 $ref: /schemas/types.yaml#/definitions/phandle-array
70 - items:
71 - description: The 'gpr' is the phandle to general purpose register node.
72 - description: The 'req_gpr' is the gpr register offset containing
79 interconnect-names:
83 $ref: /schemas/graph.yaml#/properties/ports
87 $ref: /schemas/graph.yaml#/$defs/port-base
90 Input port node, single endpoint describing the CSI-2 transmitter.
94 $ref: video-interfaces.yaml#
98 data-lanes:
101 - const: 1
102 - const: 2
103 - const: 3
104 - const: 4
107 - data-lanes
110 $ref: /schemas/graph.yaml#/properties/port
115 - port@0
116 - port@1
119 - compatible
120 - reg
121 - clocks
122 - clock-names
123 - power-domains
124 - resets
125 - ports
128 - if:
133 - fsl,imx8qxp-mipi-csi2
147 - fsl,mipi-phy-gpr
152 - |
153 #include <dt-bindings/clock/imx8mq-clock.h>
154 #include <dt-bindings/interconnect/imx8mq.h>
155 #include <dt-bindings/reset/imx8mq-reset.h>
158 compatible = "fsl,imx8mq-mipi-csi2";
160 clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
161 <&clk IMX8MQ_CLK_CSI1_ESC>,
162 <&clk IMX8MQ_CLK_CSI1_PHY_REF>;
163 clock-names = "core", "esc", "ui";
164 assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
165 <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
166 <&clk IMX8MQ_CLK_CSI1_ESC>;
167 assigned-clock-rates = <266000000>, <200000000>, <66000000>;
168 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
169 <&clk IMX8MQ_SYS2_PLL_1000M>,
170 <&clk IMX8MQ_SYS1_PLL_800M>;
171 power-domains = <&pgc_mipi_csi1>;
175 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
177 interconnect-names = "dram";
180 #address-cells = <1>;
181 #size-cells = <0>;
187 remote-endpoint = <&imx477_out>;
188 data-lanes = <1 2 3 4>;
196 remote-endpoint = <&csi_in>;