Lines Matching +full:mt8173 +full:- +full:mmsys

6 - compatible: "mediatek,mt8173-mdp"
7 - mediatek,vpu: the node of video processor unit, see
8   Documentation/devicetree/bindings/media/mediatek-vpu.txt for details.
11 - compatible: Should be one of
12         "mediatek,mt8173-mdp-rdma"  - read DMA
13         "mediatek,mt8173-mdp-rsz"   - resizer
14         "mediatek,mt8173-mdp-wdma"  - write DMA
15         "mediatek,mt8173-mdp-wrot"  - write DMA with rotation
16 - reg: Physical base address and length of the function block register space
17 - clocks: device clocks, see
18   Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
19 - power-domains: a phandle to the power domain, see
23 - compatible: Should be one of
24         "mediatek,mt8173-mdp-rdma"
25         "mediatek,mt8173-mdp-wdma"
26         "mediatek,mt8173-mdp-wrot"
27 - iommus: should point to the respective IOMMU block with master port as
33 		compatible = "mediatek,mt8173-mdp-rdma";
34 			     "mediatek,mt8173-mdp";
36 		clocks = <&mmsys CLK_MM_MDP_RDMA0>,
37 			 <&mmsys CLK_MM_MUTEX_32K>;
38 		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
44 		compatible = "mediatek,mt8173-mdp-rdma";
46 		clocks = <&mmsys CLK_MM_MDP_RDMA1>,
47 			 <&mmsys CLK_MM_MUTEX_32K>;
48 		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
53 		compatible = "mediatek,mt8173-mdp-rsz";
55 		clocks = <&mmsys CLK_MM_MDP_RSZ0>;
56 		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
60 		compatible = "mediatek,mt8173-mdp-rsz";
62 		clocks = <&mmsys CLK_MM_MDP_RSZ1>;
63 		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
67 		compatible = "mediatek,mt8173-mdp-rsz";
69 		clocks = <&mmsys CLK_MM_MDP_RSZ2>;
70 		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
74 		compatible = "mediatek,mt8173-mdp-wdma";
76 		clocks = <&mmsys CLK_MM_MDP_WDMA>;
77 		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
82 		compatible = "mediatek,mt8173-mdp-wrot";
84 		clocks = <&mmsys CLK_MM_MDP_WROT0>;
85 		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
90 		compatible = "mediatek,mt8173-mdp-wrot";
92 		clocks = <&mmsys CLK_MM_MDP_WROT1>;
93 		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;