Lines Matching +full:mt8192 +full:- +full:vcodec +full:- +full:dec
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yunfei Dong <yunfei.dong@mediatek.com>
20 +------------------------------------------------+-------------------------------------+
22 | input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
24 +------------||-------------||-------------------+---------------------||--------------+
26 -------------||-------------||-------------------|---------------------||---------------
27 ||<------------||----------------HW index---------------->|| <child>
29 +-------------------------------------------------------------+
33 +-------------------------------------------------------------+
53 mt8192: lat HW + core HW
58 - mediatek,mt8192-vcodec-dec
59 - mediatek,mt8186-vcodec-dec
60 - mediatek,mt8188-vcodec-dec
61 - mediatek,mt8195-vcodec-dec
66 - description: VDEC_SYS register space
67 - description: VDEC_RACING_CTRL register space
82 "#address-cells":
85 "#size-cells":
92 '^video-codec@[0-9a-f]+$':
98 - mediatek,mtk-vcodec-core
99 - mediatek,mtk-vcodec-lat
100 - mediatek,mtk-vcodec-lat-soc
120 clock-names:
124 assigned-clocks:
127 assigned-clock-parents:
130 power-domains:
134 - compatible
135 - reg
136 - iommus
137 - clocks
138 - clock-names
139 - assigned-clocks
140 - assigned-clock-parents
141 - power-domains
146 - compatible
147 - reg
148 - iommus
149 - mediatek,scp
150 - ranges
157 - mediatek,mtk-vcodec-core
158 - mediatek,mtk-vcodec-lat
162 - interrupts
165 - if:
170 - mediatek,mt8192-vcodec-dec
173 clock-names:
175 - const: sel
176 - const: soc-vdec
177 - const: soc-lat
178 - const: vdec
179 - const: top
181 - if:
186 - mediatek,mt8195-vcodec-dec
189 clock-names:
191 - const: sel
192 - const: vdec
193 - const: lat
194 - const: top
199 - |
200 #include <dt-bindings/interrupt-controller/arm-gic.h>
201 #include <dt-bindings/memory/mt8192-larb-port.h>
202 #include <dt-bindings/interrupt-controller/irq.h>
203 #include <dt-bindings/clock/mt8192-clk.h>
204 #include <dt-bindings/power/mt8192-power.h>
207 #address-cells = <2>;
208 #size-cells = <2>;
211 video-codec@16000000 {
212 compatible = "mediatek,mt8192-vcodec-dec";
215 #address-cells = <2>;
216 #size-cells = <2>;
219 video-codec@10000 {
220 compatible = "mediatek,mtk-vcodec-lat";
236 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
237 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
238 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
239 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
242 video-codec@25000 {
243 compatible = "mediatek,mtk-vcodec-core";
262 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
263 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
264 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
265 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;