Lines Matching +full:mt8183 +full:- +full:power
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yunfei Dong <yunfei.dong@mediatek.com>
20 - mediatek,mt8173-vcodec-dec
21 - mediatek,mt8183-vcodec-dec
27 reg-names:
29 - const: misc
30 - const: ld
31 - const: top
32 - const: cm
33 - const: ad
34 - const: av
35 - const: pp
36 - const: hwd
37 - const: hwq
38 - const: hwb
39 - const: hwg
48 clock-names:
52 assigned-clocks: true
54 assigned-clock-parents: true
56 assigned-clock-rates: true
58 power-domains:
83 - compatible
84 - reg
85 - interrupts
86 - clocks
87 - clock-names
88 - iommus
89 - mediatek,vdecsys
92 - if:
97 - mediatek,mt8183-vcodec-dec
101 - mediatek,scp
108 clock-names:
110 - const: vdec
112 - if:
117 - mediatek,mt8173-vcodec-dec
121 - mediatek,vpu
128 clock-names:
130 - const: vcodecpll
131 - const: univpll_d2
132 - const: clk_cci400_sel
133 - const: vdec_sel
134 - const: vdecpll
135 - const: vencpll
136 - const: venc_lt_sel
137 - const: vdec_bus_clk_src
142 - |
143 #include <dt-bindings/interrupt-controller/arm-gic.h>
144 #include <dt-bindings/clock/mt8173-clk.h>
145 #include <dt-bindings/memory/mt8173-larb-port.h>
146 #include <dt-bindings/interrupt-controller/irq.h>
147 #include <dt-bindings/power/mt8173-power.h>
150 compatible = "mediatek,mt8173-vcodec-dec";
173 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
182 clock-names = "vcodecpll",
190 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
195 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
198 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;