Lines Matching +full:imx6sx +full:- +full:mu
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ming Qian <ming.qian@nxp.com>
12 - Shijie Qin <shijie.qin@nxp.com>
14 description: |-
20 pattern: "^vpu@[0-9a-f]+$"
24 - enum:
25 - nxp,imx8qm-vpu
26 - nxp,imx8qxp-vpu
31 power-domains:
34 "#address-cells":
37 "#size-cells":
43 "^mailbox@[0-9a-f]+$":
45 Each vpu encoder or decoder correspond a MU, which used for communication
47 $ref: /schemas/mailbox/fsl,mu.yaml#
50 "^vpu-core@[0-9a-f]+$":
60 - enum:
61 - nxp,imx8q-vpu-decoder
62 - nxp,imx8q-vpu-encoder
67 power-domains:
70 mbox-names:
72 - const: tx0
73 - const: tx1
74 - const: rx
78 List of phandle of 2 MU channels for tx, 1 MU channel for rx.
81 memory-region:
86 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
88 - description: region reserved for firmware image sections.
89 - description: region used for RPC shared memory between firmware and
93 - compatible
94 - reg
95 - power-domains
96 - mbox-names
97 - mboxes
98 - memory-region
103 - compatible
104 - reg
105 - power-domains
111 - |
112 #include <dt-bindings/firmware/imx/rsrc.h>
115 compatible = "nxp,imx8qm-vpu";
118 #address-cells = <1>;
119 #size-cells = <1>;
120 power-domains = <&pd IMX_SC_R_VPU>;
123 compatible = "fsl,imx6sx-mu";
126 #mbox-cells = <2>;
127 power-domains = <&pd IMX_SC_R_VPU_MU_0>;
131 compatible = "fsl,imx6sx-mu";
134 #mbox-cells = <2>;
135 power-domains = <&pd IMX_SC_R_VPU_MU_1>;
139 compatible = "fsl,imx6sx-mu";
142 #mbox-cells = <2>;
143 power-domains = <&pd IMX_SC_R_VPU_MU_2>;
146 vpu_core0: vpu-core@2d080000 {
147 compatible = "nxp,imx8q-vpu-decoder";
149 power-domains = <&pd IMX_SC_R_VPU_DEC_0>;
150 mbox-names = "tx0", "tx1", "rx";
154 memory-region = <&decoder_boot>, <&decoder_rpc>;
157 vpu_core1: vpu-core@2d090000 {
158 compatible = "nxp,imx8q-vpu-encoder";
160 power-domains = <&pd IMX_SC_R_VPU_ENC_0>;
161 mbox-names = "tx0", "tx1", "rx";
165 memory-region = <&encoder1_boot>, <&encoder1_rpc>;
168 vpu_core2: vpu-core@2d0a0000 {
170 compatible = "nxp,imx8q-vpu-encoder";
171 power-domains = <&pd IMX_SC_R_VPU_ENC_1>;
172 mbox-names = "tx0", "tx1", "rx";
176 memory-region = <&encoder2_boot>, <&encoder2_rpc>;