Lines Matching +full:smi +full:- +full:larb
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yong Wu <yong.wu@mediatek.com>
16 ARM Short-Descriptor translation table format for address translation.
24 +--------+
26 gals0-rx gals1-rx (Global Async Local Sync rx)
29 gals0-tx gals1-tx (Global Async Local Sync tx)
31 +--------+
33 SMI Common(Smart Multimedia Interface Common)
35 +----------------+-------
37 | gals-rx There may be GALS in some larbs.
40 | gals-tx
42 SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb).
46 +-----+-----+ +----+----+
48 | | |... | | | ... There are different ports in each larb.
52 As above, The Multimedia HW will go through SMI and M4U while it
53 access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
54 smi local arbiter and smi common. It will control whether the Multimedia
56 directly with EMI. And also SMI help control the power domain and clocks for
59 Normally we specify a local arbiter(larb) for each multimedia HW
61 in each larb. Take a example, There are many ports like MC, PP, VLD in the
65 smi-common and m4u, and additional GALS module between smi-larb and
66 smi-common. GALS can been seen as a "asynchronous fifo" which could help
72 - enum:
73 - mediatek,mt2701-m4u # generation one
74 - mediatek,mt2712-m4u # generation two
75 - mediatek,mt6779-m4u # generation two
76 - mediatek,mt6795-m4u # generation two
77 - mediatek,mt6893-iommu-mm # generation two
78 - mediatek,mt8167-m4u # generation two
79 - mediatek,mt8173-m4u # generation two
80 - mediatek,mt8183-m4u # generation two
81 - mediatek,mt8186-iommu-mm # generation two
82 - mediatek,mt8188-iommu-vdo # generation two
83 - mediatek,mt8188-iommu-vpp # generation two
84 - mediatek,mt8188-iommu-infra # generation two
85 - mediatek,mt8192-m4u # generation two
86 - mediatek,mt8195-iommu-vdo # generation two
87 - mediatek,mt8195-iommu-vpp # generation two
88 - mediatek,mt8195-iommu-infra # generation two
89 - mediatek,mt8365-m4u # generation two
91 - description: mt7623 generation one
93 - const: mediatek,mt7623-m4u
94 - const: mediatek,mt2701-m4u
104 - description: bclk is the block clock.
106 clock-names:
108 - const: bclk
115 $ref: /schemas/types.yaml#/definitions/phandle-array
122 Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort
125 '#iommu-cells':
130 dt-binding/memory/mediatek,mt8188-memory-port.h for mt8188,
131 dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623,
132 dt-binding/memory/mt2712-larb-port.h for mt2712,
133 dt-binding/memory/mt6779-larb-port.h for mt6779,
134 dt-binding/memory/mt6795-larb-port.h for mt6795,
135 dt-binding/memory/mediatek,mt6893-memory-port.h for mt6893,
136 dt-binding/memory/mt8167-larb-port.h for mt8167,
137 dt-binding/memory/mt8173-larb-port.h for mt8173,
138 dt-binding/memory/mt8183-larb-port.h for mt8183,
139 dt-binding/memory/mt8186-memory-port.h for mt8186,
140 dt-binding/memory/mt8192-larb-port.h for mt8192.
141 dt-binding/memory/mt8195-memory-port.h for mt8195.
142 dt-binding/memory/mediatek,mt8365-larb-port.h for mt8365.
144 power-domains:
148 - compatible
149 - reg
150 - interrupts
151 - '#iommu-cells'
154 - if:
159 - mediatek,mt2701-m4u
160 - mediatek,mt2712-m4u
161 - mediatek,mt6795-m4u
162 - mediatek,mt6893-iommu-mm
163 - mediatek,mt8173-m4u
164 - mediatek,mt8186-iommu-mm
165 - mediatek,mt8188-iommu-vdo
166 - mediatek,mt8188-iommu-vpp
167 - mediatek,mt8192-m4u
168 - mediatek,mt8195-iommu-vdo
169 - mediatek,mt8195-iommu-vpp
173 - clocks
175 - if:
179 - mediatek,mt6893-iommu-mm
180 - mediatek,mt8186-iommu-mm
181 - mediatek,mt8188-iommu-vdo
182 - mediatek,mt8188-iommu-vpp
183 - mediatek,mt8192-m4u
184 - mediatek,mt8195-iommu-vdo
185 - mediatek,mt8195-iommu-vpp
189 - power-domains
191 - if:
196 - mediatek,mt2712-m4u
197 - mediatek,mt6795-m4u
198 - mediatek,mt8173-m4u
202 - mediatek,infracfg
204 - if: # The IOMMUs don't have larbs.
210 - mediatek,mt8188-iommu-infra
211 - mediatek,mt8195-iommu-infra
215 - mediatek,larbs
220 - |
221 #include <dt-bindings/clock/mt8173-clk.h>
222 #include <dt-bindings/interrupt-controller/arm-gic.h>
225 compatible = "mediatek,mt8173-m4u";
229 clock-names = "bclk";
233 #iommu-cells = <1>;