Lines Matching +full:use +full:- +full:cases

13   Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
34 "dma-ranges" property that describes how the physical address space of the
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
39 --------------------
40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
44 the specific IOMMU. Below are a few examples of typical use-cases:
46 - #iommu-cells = <0>: Single master IOMMU devices are not configurable and
50   be multi-master yet only expose a single master in a given configuration.
51   In such cases the number of cells will usually be 1 as in the next case.
52 - #iommu-cells = <1>: Multiple master IOMMU devices may need to be configured
53   in order to enable translation for a given master. In such cases the single
54   address cell corresponds to the master device's ID. In some cases more than
56 - #iommu-cells = <4>: Some IOMMU devices allow the DMA window for masters to
62 Note that these are merely examples and real-world use-cases may use different
74 --------------------
75 - iommus: A list of phandle and IOMMU specifier pairs that describe the IOMMU
80 be used for address translation. If a "dma-ranges" property exists in the
82 referenced IOMMU is disabled, in which case the "dma-ranges" property of the
85 have a means to turn off translation. But it is invalid in such cases to
90 --------------------
91 - pasid-num-bits: Some masters support multiple address spaces for DMA, by
95 - dma-can-stall: When present, the master can wait for a transaction to
102   having to either put back-pressure on the master, or abort new faulting
105   Firmware has to opt-in stalling, because most buses and masters don't
117 One possible extension to the above is to use an "iommus" property along with
118 a "dma-ranges" property in a bus device node (such as PCI host bridges). This
121 requirements of that use-case haven't been fully determined yet. Implementing
129 Single-master IOMMU:
130 --------------------
133 		#iommu-cells = <0>;
140 Multiple-master IOMMU with fixed associations:
141 ----------------------------------------------
143 	/* multiple-master IOMMU */
153 		#iommu-cells = <0>;
168 Multiple-master IOMMU:
169 ----------------------
173 		#iommu-cells = <1>;
186 Multiple-master IOMMU with configurable DMA window:
187 ---------------------------------------------------
199 			#iommu-cells = <4>;