Lines Matching +full:firmware +full:- +full:phandle

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
10   - Anup Patel <anup@brainfault.org>
13   The RISC-V advanced interrupt architecture (AIA) defines an advanced
15   in a RISC-V platform. The RISC-V AIA specification can be found at
16   https://github.com/riscv/riscv-aia.
18   The RISC-V APLIC is implemented as hierarchical APLIC domains where all
24   - $ref: /schemas/interrupt-controller.yaml#
29       - enum:
30           - qemu,aplic
31       - const: riscv,aplic
36   interrupt-controller: true
38   "#interrupt-cells":
41   interrupts-extended:
46       RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-intc
47       node, which has a CPU node (i.e. RISC-V HART) as parent.
49   msi-parent:
52       message signaled interrupt controller (IMSIC). If both "msi-parent" and
53       "interrupts-extended" properties are present then it means the APLIC
57   riscv,num-sources:
66     $ref: /schemas/types.yaml#/definitions/phandle-array
75       index is used by firmware to delegate interrupts from the given APLIC
79     $ref: /schemas/types.yaml#/definitions/phandle-array
84         - description: child APLIC domain phandle
85         - description: first interrupt number of the parent APLIC domain (inclusive)
86         - description: last interrupt number of the parent APLIC domain (inclusive)
89       of child APLIC domain phandle, first interrupt number of the parent
91       Firmware must configure interrupt delegation registers based on
98   - compatible
99   - reg
100   - interrupt-controller
101   - "#interrupt-cells"
102   - riscv,num-sources
105   - required:
106       - interrupts-extended
107   - required:
108       - msi-parent
113   - |
116     interrupt-controller@c000000 {
118       interrupts-extended = <&cpu1_intc 11>,
123       interrupt-controller;
124       #interrupt-cells = <2>;
125       riscv,num-sources = <63>;
130     aplic1: interrupt-controller@d000000 {
132       interrupts-extended = <&cpu1_intc 9>,
135       interrupt-controller;
136       #interrupt-cells = <2>;
137       riscv,num-sources = <63>;
140     aplic2: interrupt-controller@e000000 {
142       interrupts-extended = <&cpu3_intc 9>,
145       interrupt-controller;
146       #interrupt-cells = <2>;
147       riscv,num-sources = <63>;
150   - |
153     interrupt-controller@c000000 {
155       msi-parent = <&imsic_mlevel>;
157       interrupt-controller;
158       #interrupt-cells = <2>;
159       riscv,num-sources = <63>;
164     aplic3: interrupt-controller@d000000 {
166       msi-parent = <&imsic_slevel>;
168       interrupt-controller;
169       #interrupt-cells = <2>;
170       riscv,num-sources = <63>;