Lines Matching +full:gic +full:- +full:timer

1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Paul Burton <paulburton@kernel.org>
11   - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
14   The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
15   It also supports local (per-processor) interrupts and software-generated
16   interrupts which can be used as IPIs. The GIC also includes a free-running
17   global timer, per-CPU count/compare timers, and a watchdog.
21     const: mti,gic
23   "#interrupt-cells":
27       file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
28       GIC interrupt number. The 3d cell encodes the interrupt flags setting up
30       'dt-bindings/interrupt-controller/irq.h'.
34       Base address and length of the GIC registers space. If not present,
38   interrupt-controller: true
40   mti,reserved-cpu-vectors:
42       Specifies the list of CPU interrupt vectors to which the GIC may not
45     $ref: /schemas/types.yaml#/definitions/uint32-array
53   mti,reserved-ipi-vectors:
55       Specifies the range of GIC interrupts that are reserved for IPIs.
59     $ref: /schemas/types.yaml#/definitions/uint32-array
61       - minimum: 0
63       - minimum: 2
66   timer:
69       MIPS GIC includes a free-running global timer, per-CPU count/compare
70       timers, and a watchdog. Currently only the GIC Timer is supported.
73         const: mti,gic-timer
77           Interrupt for the GIC local timer, so normally it's suppose to be of
84       clock-frequency: true
87       - compatible
88       - interrupts
91       - required:
92           - clocks
93       - required:
94           - clock-frequency
101   - compatible
102   - "#interrupt-cells"
103   - interrupt-controller
106   - |
107     #include <dt-bindings/interrupt-controller/mips-gic.h>
108     #include <dt-bindings/interrupt-controller/irq.h>
110     interrupt-controller@1bdc0000 {
111       compatible = "mti,gic";
113       interrupt-controller;
114       #interrupt-cells = <3>;
115       mti,reserved-cpu-vectors = <7>;
116       mti,reserved-ipi-vectors = <40 8>;
118       timer {
119         compatible = "mti,gic-timer";
121         clock-frequency = <50000000>;
124   - |
125     #include <dt-bindings/interrupt-controller/mips-gic.h>
126     #include <dt-bindings/interrupt-controller/irq.h>
128     interrupt-controller@1bdc0000 {
129       compatible = "mti,gic";
131       interrupt-controller;
132       #interrupt-cells = <3>;
134       timer {
135         compatible = "mti,gic-timer";
140   - |
141     interrupt-controller {
142       compatible = "mti,gic";
143       interrupt-controller;
144       #interrupt-cells = <3>;