Lines Matching +full:msi +full:- +full:address +full:- +full:64
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mpic-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale MSI interrupt controller
10 The Freescale hypervisor and msi-address-64
11 -------------------------------------------
14 Freescale MSI driver calculates the address of MSIIR (in the MSI register
15 block) and sets that address as the MSI message address.
21 The ATMU is programmed with the guest physical address, and the PAMU
22 intercepts transactions and reroutes them to the true physical address.
30 subwindow can have its own address mapping ("guest physical" to "true
32 means they cannot be located at just any address. Because of these
39 this. The address specified in the msi-address-64 property is the PCI
40 address of MSIIR. The hypervisor configures the PAMU to map that address to
41 the true physical address of MSIIR.
44 - J. Neuschäfer <j.ne@posteo.net>
49 - enum:
50 - fsl,mpic-msi
51 - fsl,mpic-msi-v4.3
52 - fsl,ipic-msi
53 - fsl,vmpic-msi
54 - fsl,vmpic-msi-v4.3
55 - items:
56 - enum:
57 - fsl,mpc8572-msi
58 - fsl,mpc8610-msi
59 - fsl,mpc8641-msi
60 - const: fsl,mpic-msi
65 - description: Address and length of the shared message interrupt
67 - description: Address of aliased MSIIR or MSIIR1 register for platforms
69 added because different MSI group has different MSIIR1 offset.
77 sensitive. If msi-available-ranges is present, only the interrupts that
80 msi-available-ranges:
81 $ref: /schemas/types.yaml#/definitions/uint32-matrix
84 - description: First MSI interrupt in this range
85 - description: Number of MSI interrupts in this range
87 Define which MSI interrupt can be used in the 256 MSI interrupts.
88 If not specified, all the MSI interrupts can be used.
90 splitting an individual MSI register or the associated PIC interrupt).
92 msi-address-64:
95 64-bit PCI address of the MSIIR register. The MSIIR register is used for
96 MSI messaging. The address of MSIIR in PCI address space is the MSI
97 message address.
100 has created an alternate mapping for the MSIR block. See the top-level
104 - compatible
105 - reg
106 - interrupts
109 - if:
114 - fsl,mpic-msi-v4.3
115 - fsl,vmpic-msi-v4.3
126 msi-available-ranges: false
142 - |
143 msi@41600 {
144 compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
146 msi-available-ranges = <0 0x100>;
151 - |
152 msi@41600 {
153 compatible = "fsl,mpic-msi-v4.3";