Lines Matching +full:valid +full:- +full:wakeup +full:- +full:mask

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7038-style Level 1 interrupt controller
11   directly to one of the HW INT lines on each CPU.  Every BCM7xxx set-top chip
16    - 64, 96, 128, or 160 incoming level IRQ lines
18    - Most onchip peripherals are wired directly to an L1 input
20    - A separate instance of the register set for each CPU, allowing individual
23    - Atomic mask/unmask operations
25    - No polarity/level/edge settings
27    - No FIFO or priority encoder logic; software is expected to read all
28      2-5 status words to determine which IRQs are pending
30    If multiple reg ranges and interrupt-parent entries are present on an SMP
33    reg range and one interrupt-parent is needed.
36   - Florian Fainelli <f.fainelli@gmail.com>
39   - $ref: /schemas/interrupt-controller.yaml#
43     const: brcm,bcm7038-l1-intc
50   interrupt-controller: true
52   "#interrupt-cells":
57      Specifies the interrupt line(s) in the interrupt-parent controller node;
58      valid values depend on the type of parent interrupt controller
60   brcm,irq-can-wake:
64       wakeup source for system suspend/resume.
66   brcm,int-fwd-mask:
67     $ref: /schemas/types.yaml#/definitions/uint32-array
69       If present, a bit mask to indicate which interrupts have already been
71       have one 32-bit word per status/set/clear/mask group.
74   - compatible
75   - reg
76   - interrupt-controller
77   - "#interrupt-cells"
78   - interrupts
83   - |
84     periph_intc: interrupt-controller@1041a400 {
85       compatible = "brcm,bcm7038-l1-intc";
87       interrupt-controller;
88       #interrupt-cells = <1>;
89       interrupt-parent = <&cpu_intc>;