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1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm6345-l1-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM6345-style Level 1 interrupt controller
10   - Simon Arlott <simon@octiron.net>
18     - 32, 64 or 128 incoming level IRQ lines
20     - Most onchip peripherals are wired directly to an L1 input
22     - A separate instance of the register set for each CPU, allowing individual
25     - Contains one or more enable/status word pairs per CPU
27     - No atomic set/clear operations
29     - No polarity/level/edge settings
31     - No FIFO or priority encoder logic; software is expected to read all
32       2-4 status words to determine which IRQs are pending
34   If multiple reg ranges and interrupt-parent entries are present on an SMP
37   reg range and one interrupt-parent is needed.
44     const: brcm,bcm6345-l1-intc
51   interrupt-controller: true
53   "#interrupt-cells":
62   - compatible
63   - reg
64   - interrupt-controller
65   - '#interrupt-cells'
66   - interrupts
71   - |
72     interrupt-controller@10000000 {
73         compatible = "brcm,bcm6345-l1-intc";
77         interrupt-controller;
78         #interrupt-cells = <1>;