Lines Matching +full:machine +full:- +full:mode
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Andes machine-level software interrupt controller
12 controller (PLIC_SW). PLIC_SW directly connects to the machine-mode
13 inter-processor interrupt lines of CPUs, so RISC-V per-CPU local interrupt
15 generate machine-mode inter-processor interrupts through programming its
19 - Ben Zong-You Xie <ben717@andestech.com>
24 - enum:
25 - andestech,qilai-plicsw
26 - const: andestech,plicsw
31 interrupts-extended:
36 to a riscv,cpu-intc node, which has a riscv cpu node as parent.
41 - compatible
42 - reg
43 - interrupts-extended
46 - |
47 interrupt-controller@400000 {
48 compatible = "andestech,qilai-plicsw", "andestech,plicsw";
50 interrupts-extended = <&cpu0intc 3>,