Lines Matching +full:rpmh +full:- +full:rsc
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8650-rpmh.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8650
10 - Abel Vesa <abel.vesa@linaro.org>
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 RPMh interconnect providers support system bandwidth requirements through
15 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
16 able to communicate with the BCM through the Resource State Coordinator (RSC)
18 least one RPMh device child node pertaining to their RSC and each provider
19 can map to multiple RPMh resources.
21 See also:: include/dt-bindings/interconnect/qcom,sm8650-rpmh.h
26 - qcom,sm8650-aggre1-noc
27 - qcom,sm8650-aggre2-noc
28 - qcom,sm8650-clk-virt
29 - qcom,sm8650-cnoc-main
30 - qcom,sm8650-config-noc
31 - qcom,sm8650-gem-noc
32 - qcom,sm8650-lpass-ag-noc
33 - qcom,sm8650-lpass-lpiaon-noc
34 - qcom,sm8650-lpass-lpicx-noc
35 - qcom,sm8650-mc-virt
36 - qcom,sm8650-mmss-noc
37 - qcom,sm8650-nsp-noc
38 - qcom,sm8650-pcie-anoc
39 - qcom,sm8650-system-noc
49 - compatible
52 - $ref: qcom,rpmh-common.yaml#
53 - if:
58 - qcom,sm8650-clk-virt
59 - qcom,sm8650-mc-virt
65 - reg
67 - if:
72 - qcom,sm8650-pcie-anoc
77 - description: aggre-NOC PCIe AXI clock
78 - description: cfg-NOC PCIe a-NOC AHB clock
80 - if:
85 - qcom,sm8650-aggre1-noc
90 - description: aggre UFS PHY AXI clock
91 - description: aggre USB3 PRIM AXI clock
93 - if:
98 - qcom,sm8650-aggre2-noc
103 - description: RPMH CC IPA clock
105 - if:
110 - qcom,sm8650-aggre1-noc
111 - qcom,sm8650-aggre2-noc
112 - qcom,sm8650-pcie-anoc
115 - clocks
123 - |
124 clk_virt: interconnect-0 {
125 compatible = "qcom,sm8650-clk-virt";
126 #interconnect-cells = <2>;
127 qcom,bcm-voters = <&apps_bcm_voter>;
131 compatible = "qcom,sm8650-aggre1-noc";
133 #interconnect-cells = <2>;
135 qcom,bcm-voters = <&apps_bcm_voter>;