Lines Matching +full:default +full:- +full:mode
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
31 '#clock-cells':
34 clock-output-names:
41 adi,channel-spacing:
46 adi,power-up-frequency:
51 adi,reference-div-factor:
54 If set the driver skips dynamic calculation and uses this default
57 adi,reference-doubler-enable:
61 adi,reference-div2-enable:
65 adi,phase-detector-polarity-positive-enable:
67 description: Enables positive phase detector polarity. Default negative.
69 adi,lock-detect-precision-6ns-enable:
71 description: Enables 6ns lock detect precision. Default = 10ns.
73 adi,lock-detect-function-integer-n-enable:
76 Enables lock detect for integer-N mode. Default = factional-N mode.
78 adi,charge-pump-current:
80 description: Charge pump current in mA. Default = 2500mA.
82 adi,muxout-select:
89 0: Three-State Output (default)
92 3: R-Counter output
93 4: N-Divider output
97 adi,low-spur-mode-enable:
99 description: Enables low spur mode. Default = Low noise mode.
101 adi,cycle-slip-reduction-enable:
105 adi,charge-cancellation-enable:
108 Enabled charge pump charge cancellation for integer-N modes.
110 adi,anti-backlash-3ns-enable:
113 Enables 3ns antibacklash pulse width for integer-N modes.
115 adi,band-select-clock-mode-high-enable:
119 adi,12bit-clk-divider:
122 Clock divider value used when adi,12bit-clkdiv-mode != 0
124 adi,clk-divider-mode:
128 Valid values for the clkdiv mode are:
129 0: Clock divider off (default)
133 adi,aux-output-enable:
137 adi,aux-output-fundamental-enable:
141 Default = Output of RF dividers.
143 adi,mute-till-lock-enable:
145 description: Enables Mute-Till-Lock-Detect function.
147 adi,output-power:
152 Valid values for the power mode are:
153 0: -4dBm (default)
154 1: -1dBm
158 adi,aux-output-power:
163 Valid values for the power mode are:
164 0: -4dBm (default)
165 1: -1dBm
170 - compatible
171 - reg
172 - clocks
175 - $ref: /schemas/spi/spi-peripheral-props.yaml#
180 - |
182 #address-cells = <1>;
183 #size-cells = <0>;
188 spi-max-frequency = <10000000>;
190 clock-names = "clkin";
191 adi,channel-spacing = <10000>;
192 adi,power-up-frequency = <2400000000>;
193 adi,phase-detector-polarity-positive-enable;
194 adi,charge-pump-current = <2500>;
195 adi,output-power = <3>;
196 adi,mute-till-lock-enable;