Lines Matching +full:0 +full:x40012000
96 const: 0
234 "^adc@[0-9]+$":
251 - 0x0: ADC1
252 - 0x100: ADC2
253 - 0x200: ADC3 (stm32f4 only)
263 const: 0
268 - 0 for adc@0 (single adc for stm32mp13)
295 - 16 channels, numbered from 0 to 15 (for in0..in15) on stm32f4
296 - 19 channels, numbered from 0 to 18 (for in0..in18) on stm32mp13.
297 - 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and
307 <vinp vinn>, <vinp vinn>,... vinp and vinn are numbered from 0 to 19.
320 minimum: 0
324 minimum: 0
348 "^channel@([0-9]|1[0-9])$":
356 minimum: 0
368 minimum: 0
393 - 0x0
394 - 0x100
395 - 0x200
398 minimum: 0
409 minimum: 0
435 - 0x0
436 - 0x100
439 minimum: 0
450 minimum: 0
469 const: 0x0
472 const: 0
482 minimum: 0
503 reg = <0x40012000 0x400>;
505 clocks = <&rcc 0 168>;
513 #size-cells = <0>;
514 adc@0 {
517 reg = <0x0>;
518 clocks = <&rcc 0 168>;
520 interrupts = <0>;
522 dmas = <&dma2 0 0 0x400 0x0>;
532 // - channels 0 & 1 as single-ended
538 reg = <0x48003000 0x400>;
551 #size-cells = <0>;
552 adc@0 {
555 reg = <0x0>;
557 interrupts = <0>;
558 st,adc-channels = <0 1>;
561 dmas = <&dmamux1 9 0x400 0x05>;
575 reg = <0x48003000 0x400>;
588 #size-cells = <0>;
592 reg = <0x100>;
595 #size-cells = <0>;