Lines Matching +full:adc +full:- +full:channel +full:- +full:names
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L ADC
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
13 A/D Converter block is a successive approximation analog-to-digital converter
14 with a 12-bit accuracy. Up to eight analog input channels can be selected.
15 Conversions can be performed in single or repeat mode. Result of the ADC is
16 stored in a 32-bit data register corresponding to each channel.
21 - enum:
22 - renesas,r9a07g043-adc # RZ/G2UL and RZ/Five
23 - renesas,r9a07g044-adc # RZ/G2L
24 - renesas,r9a07g054-adc # RZ/V2L
25 - const: renesas,rzg2l-adc
35 - description: converter clock
36 - description: peripheral clock
38 clock-names:
40 - const: adclk
41 - const: pclk
43 power-domains:
49 reset-names:
51 - const: presetn
52 - const: adrst-n
54 '#address-cells':
57 '#size-cells':
61 - compatible
62 - reg
63 - interrupts
64 - clocks
65 - clock-names
66 - power-domains
67 - resets
68 - reset-names
71 "^channel@[0-7]$":
72 $ref: adc.yaml
75 Represents the external channels which are connected to the ADC.
80 The channel number.
83 - reg
88 - if:
92 const: renesas,r9a07g043-adc
95 "^channel@[2-7]$": false
96 "^channel@[0-1]$":
103 "^channel@[0-7]$":
112 - |
113 #include <dt-bindings/clock/r9a07g044-cpg.h>
114 #include <dt-bindings/interrupt-controller/arm-gic.h>
116 adc: adc@10059000 {
117 compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
122 clock-names = "adclk", "pclk";
123 power-domains = <&cpg>;
126 reset-names = "presetn", "adrst-n";
128 #address-cells = <1>;
129 #size-cells = <0>;
131 channel@0 {
134 channel@1 {
137 channel@2 {
140 channel@3 {
143 channel@4 {
146 channel@5 {
149 channel@6 {
152 channel@7 {