Lines Matching +full:aincom +full:- +full:supply

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11   - Michael Hennerich <michael.hennerich@analog.com>
16   https://www.analog.com/media/en/technical-documentation/data-sheets/AD7192.pdf
21       - adi,ad7190
22       - adi,ad7192
23       - adi,ad7193
24       - adi,ad7194
25       - adi,ad7195
27   "#address-cells":
30   "#size-cells":
36   spi-cpol: true
38   spi-cpha: true
44       MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK2
48   clock-names:
50       - xtal
51       - mclk
53   "#clock-cells":
61   aincom-supply:
63       AINCOM voltage supply. Analog inputs AINx are referenced to this input
64       when configured for pseudo-differential operation.
66   dvdd-supply:
67     description: DVdd voltage supply
69   avdd-supply:
70     description: AVdd voltage supply
72   vref-supply:
73     description: VRef voltage supply
75   adi,rejection-60-Hz-enable:
83   adi,refin2-pins-enable:
88   adi,buffer-enable:
97   adi,burnout-currents-enable:
110   "^channel@[0-9a-f]+$":
121       diff-channels:
129       single-channel:
132           appropriate value from 1 to 16. Negative input is connected to AINCOM.
137       - required:
138           - reg
139           - diff-channels
140       - required:
141           - reg
142           - single-channel
145   - compatible
146   - reg
147   - interrupts
148   - dvdd-supply
149   - avdd-supply
150   - vref-supply
151   - spi-cpol
152   - spi-cpha
155   - $ref: /schemas/spi/spi-peripheral-props.yaml#
156   - if:
160             - adi,ad7190
161             - adi,ad7192
162             - adi,ad7193
163             - adi,ad7195
166         "^channel@[0-9a-f]+$": false
167   - if:
169         - required:
170             - clocks
171         - required:
172             - clock-names
175         "#clock-cells": false
177         - clocks
178         - clock-names
183   - |
185         #address-cells = <1>;
186         #size-cells = <0>;
191             spi-max-frequency = <1000000>;
192             spi-cpol;
193             spi-cpha;
195             clock-names = "mclk";
197             interrupt-parent = <&gpio>;
198             aincom-supply = <&aincom>;
199             dvdd-supply = <&dvdd>;
200             avdd-supply = <&avdd>;
201             vref-supply = <&vref>;
203             adi,refin2-pins-enable;
204             adi,rejection-60-Hz-enable;
205             adi,buffer-enable;
206             adi,burnout-currents-enable;
209   - |
211         #address-cells = <1>;
212         #size-cells = <0>;
218             #address-cells = <1>;
219             #size-cells = <0>;
221             spi-max-frequency = <1000000>;
222             spi-cpol;
223             spi-cpha;
224             #clock-cells = <0>;
226             interrupt-parent = <&gpio>;
227             aincom-supply = <&aincom>;
228             dvdd-supply = <&dvdd>;
229             avdd-supply = <&avdd>;
230             vref-supply = <&vref>;
234                 diff-channels = <1 6>;
239                 single-channel = <1>;