Lines Matching +full:per +full:- +full:port +full:- +full:set
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
20 The Tegra186 GPIO controller allows software to set the IO direction of,
26 GPIO register set. These registers exist in a single contiguous block
30 Access to this set of registers is not necessary in all circumstances.
42 implemented by the SoC. Each GPIO is assigned to a port, and a port may
44 alphabetical port name and an integer GPIO name within the port. For
48 of implemented GPIOs within each port varies. GPIO registers within a
49 controller are grouped and laid out according to the port they affect.
51 The mapping from port name to the GPIO controller that implements that
52 port, and the mapping from port name to register offset within a
53 controller, are both extremely non-linear. The header file
54 <dt-bindings/gpio/tegra186-gpio.h> describes the port-level mapping. In
61 signal represents the aggregate status for all GPIOs within a set of
65 module and the sets-of-ports as "controllers".
68 each set of ports. Each GPIO may be configured to feed into a specific
69 one of the interrupt signals generated by a set-of-ports. The intent is
71 different CPUs to each handle subsets of the interrupts within a port.
72 The status of each of these per-port-set signals is reported via a
76 GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could
82 - nvidia,tegra186-gpio
83 - nvidia,tegra186-gpio-aon
84 - nvidia,tegra194-gpio
85 - nvidia,tegra194-gpio-aon
86 - nvidia,tegra234-gpio
87 - nvidia,tegra234-gpio-aon
89 reg-names:
91 - const: security
92 - const: gpio
97 - description: Security configuration registers.
98 - description: |
108 description: The interrupt outputs from the HW block, one per set of
112 gpio-controller: true
114 gpio-ranges:
117 "#gpio-cells":
122 - The first cell is the pin number.
123 See <dt-bindings/gpio/tegra186-gpio.h>.
124 - The second cell contains flags:
125 - Bit 0 specifies polarity
126 - 0: Active-high (normal).
127 - 1: Active-low (inverted).
130 interrupt-controller: true
132 "#interrupt-cells":
137 - The first cell is the GPIO number.
138 See <dt-bindings/gpio/tegra186-gpio.h>.
139 - The second cell is contains flags:
140 - Bits [3:0] indicate trigger type and level:
141 - 1: Low-to-high edge triggered.
142 - 2: High-to-low edge triggered.
143 - 4: Active high level-sensitive.
144 - 8: Active low level-sensitive.
150 - if:
155 - nvidia,tegra186-gpio
156 - nvidia,tegra194-gpio
157 - nvidia,tegra234-gpio
164 - if:
169 - nvidia,tegra186-gpio-aon
170 - nvidia,tegra194-gpio-aon
171 - nvidia,tegra234-gpio-aon
179 - compatible
180 - reg
181 - reg-names
182 - interrupts
187 - |
188 #include <dt-bindings/interrupt-controller/irq.h>
191 compatible = "nvidia,tegra186-gpio";
192 reg-names = "security", "gpio";
201 gpio-controller;
202 #gpio-cells = <2>;
203 interrupt-controller;
204 #interrupt-cells = <2>;
208 compatible = "nvidia,tegra186-gpio-aon";
209 reg-names = "security", "gpio";
213 gpio-controller;
214 #gpio-cells = <2>;
215 interrupt-controller;
216 #interrupt-cells = <2>;