Lines Matching +full:serial +full:- +full:shift +full:- +full:bits

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-stp-xway.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lantiq SoC Serial To Parallel (STP) GPIO controller
10   The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
11   peripheral controller used to drive external shift register cascades. At most
12   3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
16   - John Crispin <john@phrozen.org>
20     pattern: "^gpio@[0-9a-f]+$"
23     const: lantiq,gpio-stp-xway
28   gpio-controller: true
30   "#gpio-cells":
39       shift register cascade.
47       in the shift register cascade.
62       Use rising instead of falling edge for the shift register.
66   "^lantiq,phy[1-4]$":
68       The gphy core can control 3 bits of the gpio cascade. In the xRX200 family
69       phy[1-2] are available, in xRX330 phy[1-3] and in XRX330 phy[1-4].
75   - compatible
76   - reg
77   - gpio-controller
78   - "#gpio-cells"
83   - |
85         compatible = "lantiq,gpio-stp-xway";
87         #gpio-cells = <2>;
88         gpio-controller;
90         pinctrl-0 = <&stp_pins>;
91         pinctrl-names = "default";