Lines Matching +full:clr +full:- +full:gpios

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Linus Walleij <linus.walleij@linaro.org>
11   - Bartosz Golaszewski <brgl@bgdev.pl>
15   of set/clear-bit registers. Such controllers are common for glue logic in
16   FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
17   NAND-style parallel busses.
22       - brcm,bcm6345-gpio
23       - ni,169445-nand-gpio
24       - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
26   big-endian: true
28   '#gpio-cells':
31   gpio-controller: true
33   little-endian: true
40       of GPIOs is set by the width, with bit 0 corresponding to GPIO 0.
42       - description:
45           This register may also be used to drive GPIOs if the SET register is
47       - description:
50       - description:
55       - description:
59       - description:
64   reg-names:
69         - dat
70         - set
71         - clr
72         - dirout
73         - dirin
75   native-endian: true
77   no-output:
83   - compatible
84   - reg
85   - reg-names
86   - '#gpio-cells'
87   - gpio-controller
92   - |
94       compatible = "ni,169445-nand-gpio";
96       reg-names = "dat";
97       gpio-controller;
98       #gpio-cells = <2>;
102       compatible = "wd,mbl-gpio";
103       reg-names = "dat";
105       #gpio-cells = <2>;
106       gpio-controller;
107       no-output;
111       compatible = "brcm,bcm6345-gpio";
112       reg-names = "dirout", "dat";
114       native-endian;
115       gpio-controller;
116       #gpio-cells = <2>;