Lines Matching +full:fpga +full:- +full:1
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FPGA Region
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
18 - Supported Use Models
19 - Constraints
25 FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
26 the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
29 The documentation hits some of the high points of FPGA usage and
30 attempts to include terminology used by both major FPGA manufacturers. This
31 document isn't a replacement for any manufacturers specifications for FPGA
39 * The entire FPGA is programmed.
42 * A section of an FPGA is reprogrammed while the rest of the FPGA is not
44 * Not all FPGA's support PR.
48 * A PRR is a specific section of an FPGA reserved for reconfiguration.
49 * A base (or static) FPGA image may create a set of PRR's that later may
54 * The busses within the FPGA are split such that each region gets its own
59 * An FPGA image that is designed to be loaded into a PRR. There may be
64 FPGA Bridge
65 * FPGA Bridges gate bus signals between a host and FPGA.
66 * FPGA Bridges should be disabled while the FPGA is being programmed to
68 * FPGA bridges may be actual hardware or soft logic on an FPGA.
69 * During Full Reconfiguration, hardware bridges between the host and FPGA
73 * In some implementations, the FPGA Manager transparently handles gating the
74 buses, eliminating the need to show the hardware FPGA bridges in the
76 * An FPGA image may create a set of reprogrammable regions, each having its
77 own bridge and its own split of the busses in the FPGA.
79 FPGA Manager
80 * An FPGA Manager is a hardware block that programs an FPGA under the control
85 * An FPGA image that is designed to do full reconfiguration of the FPGA.
89 ---------------- ----------------------------------
90 | Host CPU | | FPGA |
92 | ----| | ----------- -------- |
94 | | W | | | ----------- -------- |
96 | | B |<=====>|<==| ----------- -------- |
98 | | I | | | ----------- -------- |
100 | | G | | | ----------- -------- |
102 | ----| | ----------- -------- |
104 ---------------- ----------------------------------
106 Figure 1: An FPGA set up with a base image that created three regions. Each
107 region (PRR0-2) gets its own split of the busses that is independently gated by
108 a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be
115 When a DT overlay that targets an FPGA Region is applied, the FPGA Region will
118 1. Disable appropriate FPGA bridges.
119 2. Program the FPGA using the FPGA manager.
120 3. Enable the FPGA bridges.
124 When the overlay is removed, the child nodes will be removed and the FPGA Region
128 FPGA Region
131 FPGA Regions represent FPGA's and FPGA PR regions in the device tree. An FPGA
135 * FPGA Manager
136 * FPGA Bridges
137 * image-specific information needed to the programming.
141 FPGA while an operating system is running.
143 An FPGA Region that exists in the live Device Tree reflects the current state.
144 If the live tree shows a "firmware-name" property or child nodes under an FPGA
145 Region, the FPGA already has been programmed. A DTO that targets an FPGA Region
146 and adds the "firmware-name" property is taken as a request to reprogram the
147 FPGA. After reprogramming is successful, the overlay is accepted into the live
150 The base FPGA Region in the device tree represents the FPGA and supports full
151 reconfiguration. It must include a phandle to an FPGA Manager. The base
152 FPGA region will be the child of one of the hardware bridges (the bridge that
153 allows register access) between the cpu and the FPGA. If there are more than
154 one bridge to control during FPGA programming, the region will also contain a
155 list of phandles to the additional hardware FPGA Bridges.
157 For partial reconfiguration (PR), each PR region will have an FPGA Region.
158 These FPGA regions are children of FPGA bridges which are then children of the
159 base FPGA region. The "Full Reconfiguration to add PRR's" example below shows
162 If an FPGA Region does not specify an FPGA Manager, it will inherit the FPGA
163 Manager specified by its ancestor FPGA Region. This supports both the case
164 where the same FPGA Manager is used for all of an FPGA as well the case where
165 a different FPGA Manager is used for each region.
167 FPGA Regions do not inherit their ancestor FPGA regions' bridges. This prevents
169 region is getting reconfigured (see Figure 1 above). During PR, the FPGA's
170 hardware bridges remain enabled. The PR regions' bridges will be FPGA bridges
171 within the static image of the FPGA.
177 In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and
178 a FPGA Region. The target of the Device Tree Overlay is the FPGA Region. Some
179 uses are specific to an FPGA device.
181 * No FPGA Bridges
182 In this case, the FPGA Manager which programs the FPGA also handles the
183 bridges behind the scenes. No FPGA Bridge devices are needed for full
187 In this case, there are hardware bridges between the processor and FPGA that
189 applied, the live DT must include the FPGA Manager, FPGA Bridges, and a
190 FPGA Region. The FPGA Region is the child of the bridge that allows
191 register access to the FPGA. Additional bridges may be listed in a
192 fpga-bridges property in the FPGA region or in the device tree overlay.
194 * Partial reconfiguration with bridges in the FPGA
195 In this case, the FPGA will have one or more PRR's that may be programmed
196 separately while the rest of the FPGA can remain active. To manage this,
197 bridges need to exist in the FPGA that can gate the buses going to each FPGA
199 reconfiguration can be done, a base FPGA image must be loaded which includes
200 PRR's with FPGA bridges. The device tree should have an FPGA region for each
206 It is beyond the scope of this document to fully describe all the FPGA design
207 constraints required to make partial reconfiguration work[1] [2] [3], but a few
215 FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration.
217 --
218 [1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf
219 [2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf
224 pattern: "^fpga-region(@.*|-([0-9]|[1-9][0-9]+))?$"
227 const: fpga-region
230 maxItems: 1
233 "#address-cells": true
234 "#size-cells": true
236 config-complete-timeout-us:
238 The maximum time in microseconds time for the FPGA to go to operating
241 encrypted-fpga-config:
246 external-fpga-config:
249 Set if the FPGA has already been configured prior to OS boot up.
251 firmware-name:
252 maxItems: 1
254 Should contain the name of an FPGA image file located on the firmware
256 that the FPGA has already been programmed with this image.
257 If this property is in an overlay targeting an FPGA region, it is
258 a request to program the FPGA with that image.
260 fpga-bridges:
261 $ref: /schemas/types.yaml#/definitions/phandle-array
263 Should contain a list of phandles to FPGA Bridges that must be
264 controlled during FPGA programming along with the parent FPGA bridge.
265 This property is optional if the FPGA Manager handles the bridges.
266 If the fpga-region is the child of an fpga-bridge, the list should not
269 fpga-mgr:
272 Should contain a phandle to an FPGA Manager. Child FPGA Regions
273 inherit this property from their ancestor regions. An fpga-mgr property
274 in a region will override any inherited FPGA manager.
276 partial-fpga-config:
282 region-freeze-timeout-us:
287 region-unfreeze-timeout-us:
293 - compatible
294 - fpga-mgr
300 - |
304 fpga_region0: fpga-region@0 {
305 compatible = "fpga-region";
307 #address-cells = <1>;
308 #size-cells = <1>;
309 fpga-mgr = <&fpga_mgr0>;
313 firmware-name = "zynq-gpio.bin";
315 compatible = "xlnx,xps-gpio-1.00.a";
317 gpio-controller;
318 #gpio-cells = <2>;
322 - |
326 fpga_region1: fpga-region@0 {
327 compatible = "fpga-region";
330 #address-cells = <1>;
331 #size-cells = <1>;
332 fpga-mgr = <&fpga_mgr1>;
333 fpga-bridges = <&fpga_bridge1>;
334 partial-fpga-config;
337 firmware-name = "zynq-gpio-partial.bin";
339 compatible = "fixed-factor-clock";
341 #clock-cells = <0>;
342 clock-div = <2>;
343 clock-mult = <1>;
346 compatible = "simple-bus";
347 #address-cells = <1>;
348 #size-cells = <1>;
351 compatible = "xlnx,xps-gpio-1.00.a";
353 #gpio-cells = <2>;
354 gpio-controller;