Lines Matching +full:dt +full:- +full:property
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
18 - Supported Use Models
19 - Constraints
89 ---------------- ----------------------------------
92 | ----| | ----------- -------- |
94 | | W | | | ----------- -------- |
96 | | B |<=====>|<==| ----------- -------- |
98 | | I | | | ----------- -------- |
100 | | G | | | ----------- -------- |
102 | ----| | ----------- -------- |
104 ---------------- ----------------------------------
107 region (PRR0-2) gets its own split of the busses that is independently gated by
108 a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be
115 When a DT overlay that targets an FPGA Region is applied, the FPGA Region will
137 * image-specific information needed to the programming.
144 If the live tree shows a "firmware-name" property or child nodes under an FPGA
146 and adds the "firmware-name" property is taken as a request to reprogram the
177 In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and
189 applied, the live DT must include the FPGA Manager, FPGA Bridges, and a
192 fpga-bridges property in the FPGA region or in the device tree overlay.
217 --
218 [1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf
224 pattern: "^fpga-region(@.*|-([0-9]|[1-9][0-9]+))?$"
227 const: fpga-region
233 "#address-cells": true
234 "#size-cells": true
236 config-complete-timeout-us:
241 encrypted-fpga-config:
246 external-fpga-config:
251 firmware-name:
255 search path. If this property shows up in a live device tree it indicates
257 If this property is in an overlay targeting an FPGA region, it is
260 fpga-bridges:
261 $ref: /schemas/types.yaml#/definitions/phandle-array
265 This property is optional if the FPGA Manager handles the bridges.
266 If the fpga-region is the child of an fpga-bridge, the list should not
269 fpga-mgr:
273 inherit this property from their ancestor regions. An fpga-mgr property
276 partial-fpga-config:
282 region-freeze-timeout-us:
287 region-unfreeze-timeout-us:
293 - compatible
294 - fpga-mgr
300 - |
302 * Full Reconfiguration without Bridges with DT overlay
304 fpga_region0: fpga-region@0 {
305 compatible = "fpga-region";
307 #address-cells = <1>;
308 #size-cells = <1>;
309 fpga-mgr = <&fpga_mgr0>;
312 /* DT Overlay contains: &fpga_region0 */
313 firmware-name = "zynq-gpio.bin";
315 compatible = "xlnx,xps-gpio-1.00.a";
317 gpio-controller;
318 #gpio-cells = <2>;
323 - |
327 fpga_region1: fpga-region@0 {
328 compatible = "fpga-region";
331 #address-cells = <1>;
332 #size-cells = <1>;
333 fpga-mgr = <&fpga_mgr1>;
334 fpga-bridges = <&fpga_bridge1>;
335 partial-fpga-config;
337 /* DT Overlay contains: &fpga_region1 */
338 firmware-name = "zynq-gpio-partial.bin";
340 compatible = "fixed-factor-clock";
342 #clock-cells = <0>;
343 clock-div = <2>;
344 clock-mult = <1>;
347 compatible = "simple-bus";
348 #address-cells = <1>;
349 #size-cells = <1>;
352 compatible = "xlnx,xps-gpio-1.00.a";
354 #gpio-cells = <2>;
355 gpio-controller;