Lines Matching +full:dma +full:- +full:coherent
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DMA Engine
10 The Xilinx ZynqMP DMA engine supports memory to memory transfers,
12 control and rate control support for slave/peripheral dma access.
15 - Michael Tretter <m.tretter@pengutronix.de>
16 - Harini Katakam <harini.katakam@amd.com>
17 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
20 - $ref: ../dma-controller.yaml#
23 "#dma-cells":
28 - amd,versal2-dma-1.0
29 - xlnx,zynqmp-dma-1.0
36 description: DMA channel interrupt
44 clock-names:
46 - const: clk_main
47 - const: clk_apb
49 xlnx,bus-width:
52 - 64
53 - 128
59 power-domains:
62 dma-coherent:
63 description: present if dma operations are coherent
66 - "#dma-cells"
67 - compatible
68 - reg
69 - interrupts
70 - clocks
71 - clock-names
72 - xlnx,bus-width
77 - |
78 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
80 fpd_dma_chan1: dma-controller@fd500000 {
81 compatible = "xlnx,zynqmp-dma-1.0";
83 interrupt-parent = <&gic>;
85 #dma-cells = <1>;
86 clock-names = "clk_main", "clk_apb";
88 xlnx,bus-width = <128>;
89 dma-coherent;